Patents by Inventor Xiaohua Fan

Xiaohua Fan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240111722
    Abstract: Deleting directories in a virtual distributed file system (VDFS), and non-virtual file systems, involves changing the name of a selected directory to a unique object identifier (UID) and moving the selected directory, named according to the UID, to a deletion target directory. A recursive process, implemented using a background deletion thread, starts in the current directory and identifies objects in the current directory. For an object that is a file or an empty directory, the object is added to a deletion queue. For an object that is a directory that is not empty, the recursion drops down into that directory as the new current directory. When the recursion has exhausted the selected directory, or some maximum object count has been reached, the objects identified in the deletion queue are deleted. This approach can also be used for file operations other than deletion, such as compression, encryption, and hashing.
    Type: Application
    Filed: November 21, 2022
    Publication date: April 4, 2024
    Inventors: Xiaohua FAN, Zhaohui GUO, Wenguang WANG, Kiran PATIL, Abhay Kumar JAIN
  • Publication number: 20240021821
    Abstract: The present disclosure relates to a graphite negative electrode material and a preparation method thereof and a lithium ion battery, wherein the graphite negative electrode material includes spherical graphite and a carbon coating layer, the carbon coating layer includes an M element-containing modifying group, where M is at least one selected from the group consisting of B, N, and P. The preparation method of a graphite negative electrode material includes performing a thermal polymerization treatment on a mixture containing spherical graphite, a coating agent, and a modifying additive, to obtain a precursor, wherein modifying additive includes an element M-containing compound, and M is at least one selected from the group consisting of B, N, and P; and performing a carbonization treatment on the precursor under a protective atmosphere, to obtain the graphite negative electrode material.
    Type: Application
    Filed: September 25, 2023
    Publication date: January 18, 2024
    Inventors: Xuan Wu, Xiaohua Fan, Haihui Zhou, Jianguo Ren, Xueqin He
  • Publication number: 20220189615
    Abstract: A decentralized method for generation and management of health monitoring related tasks in a hyperconverged infrastructure (HCl) environment is provided. The hosts in the HCl environment each include a health agent and a task manager. The health agent collects health results from health checks and stores the health results in a shared database that is shared by the hosts. The task manager generates a health monitoring related task in response to the health results being indicative of a change in health status, and stores the health monitoring related task in a task pool that is also shared by the hosts. Any of the hosts can obtain and execute the health monitoring related tasks in the task pool based on a task priority and load balancing criteria.
    Type: Application
    Filed: January 28, 2021
    Publication date: June 16, 2022
    Applicant: VMware, Inc.
    Inventors: Xiang YU, Yu WU, Yang YANG, Sifan LIU, Jin FENG, Xiaohua FAN
  • Patent number: 11150993
    Abstract: Computerized techniques involve dividing a plurality of entries included in an indirect block of an inode into a plurality of entry groups. Each non-null entry of the plurality of entries has one of a pointer pointing to an associated data block and an identifier specific to a byte pattern of an associated data block. The techniques further involve determining, for an entry group of the plurality of entry groups, whether entries having an identifier in the entry group all have a same predetermined identifier. The techniques further involve in response to determining that the entries having an identifier in the entry group all have the same predetermined identifier, identifying the entry group as recoverable if the indirect block is corrupted. Such techniques improve reliability and performance of a storage system.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: October 19, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Leihu Zhang, Xiaohua Fan, Hao Fang, Chen Gong, Ming Zhang
  • Patent number: 10545671
    Abstract: A method, computer program product, and computer system for receiving, at a computing device, an I/O request directed to a compressed data portion of a storage system. It may be determined whether the I/O request includes one of a first portion of information and a second portion of information. An address of the compressed data portion may be obtained via downward mapping if the I/O request includes the first portion of information. The address of the compressed data portion may be obtained via upward mapping if the I/O request includes the second portion of information. The I/O request may be executed at the compressed data portion.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: January 28, 2020
    Assignee: EMC IP Holding Company, LLC
    Inventors: Xiaohua Fan, Yaming Kuang, Walter Forrester
  • Publication number: 20190220363
    Abstract: Computerized techniques involve dividing a plurality of entries included in an indirect block of an inode into a plurality of entry groups. Each non-null entry of the plurality of entries has one of a pointer pointing to an associated data block and an identifier specific to a byte pattern of an associated data block. The techniques further involve determining, for an entry group of the plurality of entry groups, whether entries having an identifier in the entry group all have a same predetermined identifier. The techniques further involve in response to determining that the entries having an identifier in the entry group all have the same predetermined identifier, identifying the entry group as recoverable if the indirect block is corrupted. Such techniques improve reliability and performance of a storage system.
    Type: Application
    Filed: January 16, 2019
    Publication date: July 18, 2019
    Inventors: Leihu Zhang, Xiaohua Fan, Hao Fang, Chen Gong, Ming Zhang
  • Patent number: 10114731
    Abstract: An improved method of analyzing software issues may include retrieving and storing selected data elements from the operating system kernel data prior to performing a memory dump. The method of retrieving the selected kernel data may include creating a thread dedicated to collecting the data and storing it in a memory location for analysis after the memory dump. The operating system kernel data may be analyzed in conjunction with the prior art dump data to identify a root cause of the software issue.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: October 30, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Xiaohua Fan, Feng Yin, Xiaogang Wang, Dazhi Dong, Binhua Lu
  • Patent number: 9329805
    Abstract: A method of verifying that a storage system is complying with best practices guide includes a software program running in host servers for determining the host server configuration parameters, and comparing the host server configuration to the storage system configuration. If a newly added best practices rule is found to be different than either the current configuration of the storage system or the host server configuration, then an alert may be generated, and sent to a storage system user or manager. In addition, a suggested change notice may be generated and transmitted to the storage system user or manager. There may also be a suggested change notice sent to the host server. Best practices rules may be stored in a data base and updated frequently.
    Type: Grant
    Filed: December 24, 2013
    Date of Patent: May 3, 2016
    Assignee: EMC Corporation
    Inventors: Xiaohua Fan, Qin Tao, Yuanjie Wu, Xiaogang Wang, Dazhi Dong
  • Patent number: 9166632
    Abstract: A receiver including a mixer, a clock generator, a plurality of capacitances, a plurality of resistances, and a controller. The mixer includes a plurality of switches. The clock generator is configured to generate clock signals to drive the plurality of switches of the mixer. The plurality of capacitances couples the clock signals to respective inputs of the plurality of switches. The plurality of resistances couples to the respective inputs of the plurality of switches. The controller is configured to output a first signal to the plurality of resistances. The first signal determines one or more attributes of the clock signals. One or more switching characteristics of the plurality of switches of the mixer are based on the one or more attributes of the clock signals.
    Type: Grant
    Filed: June 10, 2014
    Date of Patent: October 20, 2015
    Assignee: Marvell International LTD.
    Inventors: Gregory Uehara, Brian Brunn, Xiaohua Fan, Sehat Sutardja
  • Publication number: 20150186246
    Abstract: An improved method of analyzing software issues may include retrieving and storing selected data elements from the operating system kernel data prior to performing a memory dump. The method of retrieving the selected kernel data may include creating a thread dedicated to collecting the data and storing it in a memory location for analysis after the memory dump. The operating system kernel data may be analyzed in conjunction with the prior art dump data to identify a root cause of the software issue.
    Type: Application
    Filed: December 23, 2014
    Publication date: July 2, 2015
    Inventors: Xiaohua Fan, Feng Yin, Xiaogang Wang, Dazhi Dong, Binhua Lu
  • Patent number: 9042859
    Abstract: A circuit includes first and second transconductance stages that generate first and second currents, respectively, in response to an input signal. A current combiner circuit selectively couples the first current to a first output, selectively couples the second current to the first output, selectively couples the first current to a second output, and selectively couples the second current to the second output. In response to the first current being coupled to both the first and second outputs, the current combiner circuit couples the second current to both the first and second outputs. In response to the first current being decoupled from the second output, the current combiner circuit decouples the second current from both the first and second outputs. In response to the first current being decoupled from the first output, the current combiner circuit decouples the second current from both the first and second outputs.
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: May 26, 2015
    Assignee: Marvell World Trade Ltd.
    Inventors: Gregory Uehara, Xiaohua Fan
  • Patent number: 8750437
    Abstract: A receiver including a mixer configured to generate (i) a first output and (ii) a second output, a first capacitance coupled to the first output, and a second capacitance coupled to the second output, A controller is configured to program (i) the first capacitance and (ii) the second capacitance to a first capacitance value in response to operating the receiver in a first mode, and program (i) the first capacitance and (ii) the second capacitance to a second capacitance value in response to operating the receiver in a second mode. The first capacitance value determines one or more of (i) linearity, (ii) gain, and (iii) noise figure of the receiver in the first mode. The second capacitance value determines one or more of (i) linearity, (ii) gain, and (iii) noise figure of the receiver in the second mode.
    Type: Grant
    Filed: March 25, 2013
    Date of Patent: June 10, 2014
    Assignee: Marvell International Ltd.
    Inventors: Gregory Uehara, Brian Brunn, Xiaohua Fan, Sehat Sutardja
  • Patent number: 8688055
    Abstract: An amplifier integrated circuit (IC) including a push-pull amplifier having a push stage and a pull stage. A first loop of wire configured to form a first degeneration inductance of the push stage. A second loop of wire configured to form a first degeneration inductance of the pull stage. The first loop and the second loop are concentric. The first loop is connected to a reference potential. The second loop is connected to a supply voltage.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: April 1, 2014
    Assignee: Marvell World Trade Ltd.
    Inventors: Brian T. Brunn, Sehat Sutardja, Xiaohua Fan, Gregory T. Uehara
  • Publication number: 20130293303
    Abstract: A circuit includes first and second transconductance stages that generate first and second currents, respectively, in response to an input signal. A current combiner circuit selectively couples the first current to a first output, selectively couples the second current to the first output, selectively couples the first current to a second output, and selectively couples the second current to the second output. In response to the first current being coupled to both the first and second outputs, the current combiner circuit couples the second current to both the first and second outputs. In response to the first current being decoupled from the second output, the current combiner circuit decouples the second current from both the first and second outputs. In response to the first current being decoupled from the first output, the current combiner circuit decouples the second current from both the first and second outputs.
    Type: Application
    Filed: July 8, 2013
    Publication date: November 7, 2013
    Inventors: Gregory UEHARA, Xiaohua Fan
  • Patent number: 8483645
    Abstract: A circuit includes first and second transconductance stages each having an input to receive a signal, and a current combiner circuit coupled to outputs of the first and second transconductance stages. The current combiner circuit forms a path from the first transconductance stage to (i) one of a plurality of output paths or (ii) multiple output paths of the output paths. The current combiner circuit severs the second transconductance stage from the output paths when the first transconductance stage forms a path to one of the output paths. The current combiner circuit forms a path from the second transconductance stage to the multiple output paths when the first transconductance stage forms a path to the multiple output paths. The current combiner circuit couples current from the first transconductance stage to (i) a first output path or a second output path or (ii) both the first and second output paths.
    Type: Grant
    Filed: March 2, 2011
    Date of Patent: July 9, 2013
    Assignee: Marvell World Trade Ltd.
    Inventors: Gregory Uehara, Xiaohua Fan
  • Patent number: 8406358
    Abstract: A radio frequency (RF) apparatus has a receiver. The receiver includes a mixer, a clock generator, and a common mode controller. The clock generator couples to the mixer. The common mode controller couples to the outputs of mixer. The mixer, the clock generator and the common mode controller are operated collectively to program linearity and a gain of the receiver.
    Type: Grant
    Filed: February 17, 2009
    Date of Patent: March 26, 2013
    Assignee: Marvell International Ltd.
    Inventors: Gregory Uehara, Brian Brunn, Xiaohua Fan, Sehat Sutardja
  • Patent number: 8346179
    Abstract: An amplifier integrated circuit (IC) includes a push-pull configuration including a push stage and a pull stage. A first loop of wire is configured to form a first degeneration inductance of the push stage. A second loop of wire is configured to form a first degeneration inductance of the pull stage. The first and second loops are concentric.
    Type: Grant
    Filed: May 3, 2010
    Date of Patent: January 1, 2013
    Assignee: Marvell World Trade Ltd.
    Inventors: Brian Brunn, Sehat Sutardja, Xiaohua Fan, Gregory Uehara
  • Publication number: 20110217945
    Abstract: In one embodiment, the present disclosure includes a circuit comprising first and second transconductance stages that receive an RF signal and a current combiner circuit. The current combiner circuit couples current from the first transconductance stage to (i) one of a first output path or a second output path or (ii) both the first output path and second output path. The current combiner circuit decouples current from the second transconductance stage from both the first output path and second output path when the first transconductance stage couples current to one of the first output path or the second output path. The current combiner circuit couples current from the second transconductance stage to both the first output path and the second output path when the first transconductance stage couples current to both the first output path and the second output path.
    Type: Application
    Filed: March 2, 2011
    Publication date: September 8, 2011
    Inventors: Gregory Uehara, Xiaohua Fan
  • Publication number: 20100291881
    Abstract: An amplifier integrated circuit (IC) includes a push-pull configuration including a push stage and a pull stage. A first loop of wire is configured to form a first degeneration inductance of the push stage. A second loop of wire is configured to form a first degeneration inductance of the pull stage. The first and second loops are concentric.
    Type: Application
    Filed: May 3, 2010
    Publication date: November 18, 2010
    Inventors: Brian Brunn, Sehat Sutardja, Xiaohua Fan, Gregory Uehara