Abstract: Embodiments described herein relate to a method for fabricating word lines of a NAND memory. In the process for fabricating the word lines of the NAND memory, by adding a sacrificial pattern at a position close to a core layer or a sidewall of a select transistor at the edge of the word lines, the actual word line pattern is not at the outermost edge of the pattern, the pattern density of the edge word line pattern is closer to the pattern density of the middle word line pattern, the morphology and size of the edge word line are closer to the morphology and size of the middle area during core layer etching and sidewall etching, and thus the uniformity of the finally etched word lines is improved.

Abstract: The present invention provides a method for optimizing a critical dimension for double patterning for NAND flash, forming a core oxide layer on amorphous silicon layer on substrate; densifying the core oxide layer and etching it to form a core pattern; measuring CD values of the bottom and top of the core pattern; providing etching rates of a non-densified core oxide layer and a densified core oxide layer under the same etching condition; calculating the thickness of the core oxide layer required to be densified according to the CD values of the bottom and top of the core pattern and the etching rates to determine the densifying time. The present invention precisely controls the morphology and CD, and obtains a double-patterned target pattern with consistent CD sizes of a top and a bottom and a consistent bottom height, so as to improve a product yield.

Abstract: The present invention provides a method for optimizing a critical dimension for double patterning for NAND flash, forming a core oxide layer on amorphous silicon layer on substrate; densifying the core oxide layer and etching it to form a core pattern; measuring CD values of the bottom and top of the core pattern; providing etching rates of a non-densified core oxide layer and a densified core oxide layer under the same etching condition; calculating the thickness of the core oxide layer required to be densified according to the CD values of the bottom and top of the core pattern and the etching rates to determine the densifying time. The present invention precisely controls the morphology and CD, and obtains a double-patterned target pattern with consistent CD sizes of a top and a bottom and a consistent bottom height, so as to improve a product yield.

Abstract: Embodiments described herein relate to a method for fabricating word lines of a NAND memory. In the process for fabricating the word lines of the NAND memory, by adding a sacrificial pattern at a position close to a core layer or a sidewall of a select transistor at the edge of the word lines, the actual word line pattern is not at the outermost edge of the pattern, the pattern density of the edge word line pattern is closer to the pattern density of the middle word line pattern, the morphology and size of the edge word line are closer to the morphology and size of the middle area during core layer etching and sidewall etching, and thus the uniformity of the finally etched word lines is improved.