Abstract: A molecular marker combination linked to quantitative traits of tea plant caffeine content, including a SNP site 1, a SNP site 2, a SNP site 3, a SNP site 4, a SNP site 5 and a SNP site 6, which are located in tea genomes Scaffold4239:309117, Scaffold115:803980, Scaffold720:596655, Scaffold3614:66549, Scaffold349:3413816 and Scaffold920:281727, respectively, and genotypes thereof are extremely significantly correlated with the caffeine content is provided. A detection method for detecting each site, and one or more molecular marker site is used to evaluate the tea plant caffeine content.

Abstract: A molecular marker combination linked to quantitative traits of tea plant (+)-catechin content, including a SNP site 1, a SNP site 2, a SNP site 3, a SNP site 4, a SNP site 5, a SNP site 6, a SNP site 7 and a SNP site 8, which are located in tea genomes Scaffold4239:309117, Scaffold3614: 66549, Scaffold349: 3413816, Scaffold1989: 2316385, Scaffold451: 940283, Scaffold3727:442660, Scaffold115:803980 and Scaffold920:281727, respectively, and genotypes thereof are extremely significantly correlated with the (+)-catechin content is provided. A detection method for detecting each site, and one or more molecular marker site is used to evaluate the tea plant (+)-catechin content.

Abstract: The present disclosure discloses a process for producing microcrystalline alpha-alumina by microwave calcination, which relates to the production process of calcined alumina. The product of the present disclosure has stable quality. The yield of the process of the present disclosure is higher than that of the traditional kiln production method. The energy consumption during the preparation of alpha-alumina is greatly reduced, and the zero emission of harmful gases is realized.

Abstract: The OLED tiled display includes front and back lighting display units that emitting lights toward each other. The front lighting display unit includes a first substrate and a first organic light emitting device. The back lighting display unit includes a second substrate and a second organic light emitting device. The first and second light emitting devices neighbor laterally on each other, but are vertically aligned to a second extended section of the second substrate and a first extended section of the first substrate, respectively. The present invention achieves small gaps and resolves the problem of obvious gaps in an OLED tiled display by piecing together the front and back lighting display units, where the substrate of the front lighting display unit functions as encapsulation layer to the back lighting display unit, and the substrate of the back lighting display unit functions as encapsulation layer to the front lighting display unit.

Abstract: The OLED tiled display includes front and back lighting display units that emitting lights toward each other. The front lighting display unit includes a first substrate and a first organic light emitting device. The back lighting display unit includes a second substrate and a second organic light emitting device. The first and second light emitting devices neighbor laterally on each other, but are vertically aligned to a second extended section of the second substrate and a first extended section of the first substrate, respectively. The present invention achieves small gaps and resolves the problem of obvious gaps in an OLED tiled display by piecing together the front and back lighting display units, where the substrate of the front lighting display unit functions as encapsulation layer to the back lighting display unit, and the substrate of the back lighting display unit functions as encapsulation layer to the front lighting display unit.

Abstract: A method for adjusting a luminance of a RGBW liquid crystal display is provided by the disclosure. The liquid crystal display includes a RGBW sub-pixel, wherein the luminance of the W sub-pixel is achieved by adjusting one or more of width, spacing, thickness of liquid crystal cell, and number of branch of a sub-pixel electrode corresponding to the W sub-pixel, channel region at the sub-pixel electrode corresponding to the W sub-pixel, and aperture ratio at the sub-pixel electrode corresponding to the W sub-pixel. A liquid crystal display is also provided by the disclosure, and the method for adjusting the luminance of the RGBW liquid crystal display is applicable for the luminance of the W sub-pixel for achieving the adjustment of the luminance of the W sub-pixel.

Abstract: A poly-silicon thin film transistor and its manufacturing method, an array substrate and its manufacturing method, and a display device are provided. The method for manufacturing a poly-silicon thin film transistor includes forming a poly-silicon layer on a base substrate so that the poly-silicon layer includes a first poly-silicon area, second poly-silicon areas located at the both sides of the first poly-silicon area and third poly-silicon areas located at a side of the second poly-silicon areas away from the first poly-silicon area; forming a barrier layer between a gate electrode and a gate insulation layer by a dry etching method so that the barrier layer corresponds to the first poly-silicon area; and with the barrier layer as a mask doping the second poly-silicon areas to form lightly doped areas. By this method, the lightly doped areas may have the same length, and thus the problem of excessive leakage current is avoided.

Abstract: Disclosed are a TFT array substrate, a method for fabricating the same and a display device. The TFT array substrate includes a plurality of pixel units, each of the plurality of pixel units includes a common electrode (9). The common electrode (9), is comb-shaped, and includes a plurality of strip electrodes and a plurality of slits. Each of the strip electrodes is configured for reflecting light incident on the strip electrode, and each of the slits is configured for transmitting light incident on the slit. As the comb-shaped common electrode with both a reflective region and a transmissive region is formed through a single patterning process, the fabrication process is simplified and the fabrication cost and difficulty are reduced.

Abstract: A fabrication method includes preparing a base substrate, the base substrate including a pixel region and a region of gate on array (GOA); forming a pattern including a gate electrode and a pattern of an active layer on the base substrate, and forming a gate lead on the region of GOA, by a first patterning process; forming a pattern of a gate insulating layer by a second patterning process; forming a pattern including a source/drain electrode by a third patterning process; forming a pattern of a planarization layer by a fourth patterning layer; and forming a pattern including a pixel electrode by a fifth patterning layer. Here, the pattern including the gate electrode and the pattern including the active layer are formed by one patterning process, which can reduce the number of masks in the fabrication process of the array substrate, improve production efficiency and save the cost.

Abstract: A thin film transistor (TFT), a method for fabricating the same, an array substrate and a display device are provided. The TFT includes a source electrode and a drain electrode, a semiconductor active layer, a gate insulating layer and a gate electrode. The TFT further includes a light-shielding layer between the source electrode and the drain electrode. The light-shielding layer separates the source electrode and the drain electrode, and the light-shielding layer is disposed on a light incident side of the semiconductor active layer and is used to prevent the incident light from irradiating on the semiconductor active layer.

Abstract: The present invention provides a low-temperature polysilicon thin film transistor array substrate and a method of fabricating the same, and a display device. The array substrate comprises: a substrate; a polysilicon active layer provided on the substrate; a first insulation layer provided on the active layer; a plurality of gates and a gate line provided on the first insulation layer; a second insulation layer provided on the gates; a source, a drain, a data line and a pixel electrode electrically connected with the drain, which are provided on the second insulation layer, the source covers the plurality of gates. The plurality of gates are provided directly below the source, so that the leakage current is reduced and the aperture ratio of panel is improved.

Abstract: An etching time detection means and an etching time detection method for an etching device. The detection means comprises: a light wave emitter fixed on one substrate of the etching device, a light wave receiver fixed on another substrate and opposed to the light wave emitter, a detection system communicated with the light wave emitter and the light wave receiver for receiving light intensity signals and calculating etching time. With the detection means and the detection method, the automatical detection of etching time can be achieved and the deviation caused by visual observation can be effectively avoided.

Abstract: An array substrate, a manufacturing method thereof and a display device are disclosed. The array substrate comprises: a base substrate (1), thin-film transistors (TFTs), an isolation layer (10) and an organic resin layer (8) formed on the base substrate (1), and a common electrode layer (12) formed on the organic resin layer (8). The isolation layer (10) covers source electrodes (6) and drain electrodes (7) of the TFTs; the organic resin layer (8) covers the isolation layer (10) and is provided with first through holes (9) corresponding to the drain electrodes (7) of the TFTs; the isolation layer (10) is provided with second through holes (11) communicated with the first through holes (9) to expose partial drain electrodes (7); and the dimension of the second through holes (11) is greater than that of the first through holes (9).

Abstract: The present invention discloses an array substrate, a preparation method for the array substrate, and a display device, wherein the array substrate comprises a gate electrode, a gate insulation layer, an active layer, a source electrode and a drain electrode, and a pixel electrode arranged on a substrate, the active layer includes an electric conduction area, a coverage area covered by the source electrode and the drain electrode, and an exposure area surrounding the coverage area, and the pixel electrode is lapped on the upper surfaces of the drain electrode, the exposure area of the active layer, and the gate insulation layer. According to the present invention, the pixel electrode breaks in the area, with the large gradient angle, of the drain electrode caused by slip-down due to gravity can be avoided, and the lap joint for the pixel electrode and the drain electrode is effectively facilitated.

Abstract: A needle-exchangeable and self-destruction insulin syringe comprises a barrel (1), a push rod (2), a rubber piston (3) and a needle seat (4). The barrel (1) is provided with a connection needle seat (7) matched with a needle hub (5). The connection needle seat (7) is supported and fastened at the front end of the barrel by a support seat (8). The needle hub (5) is extended downwards to form a fixing ring (9). A snap ring (10) is formed at an upper end of the connection needle seat (7). The snap ring (10) is protruded into the bore of the fixing ring (9) and locked with the fixing ring (9). A large groove (13) is provided in the wall of the bore of the connection needle seat (7). The upper end of the support seat (8) is protruded into the bore of the connection needle seat (7). First elastic detents (14) are formed at the upper end of the support seat (8) and come together towards the center.

Abstract: The embodiments of the present invention provide a thin film transistor including a gate, an upper active layer, a lower active layer, an upper source, a lower source, an upper drain and a lower drain. The upper active layer and the lower active layer are disposed at an upper side and a lower side of the gate, respectively, the lower source and the lower drain are connected to the lower active layer, respectively, and the upper source and the upper drain are connected to the upper active layer, respectively. The embodiments of the present invention also provide an array substrate including the thin film transistor, a method of fabricating the array substrate, and a display device including the array substrate.

Abstract: A method of manufacturing a TFT array substrate and a TFT array substrate and a display device are provided. During a pattern of a gate layer (2), a pattern of the gate insulating layer (3) and a pattern of the active layer are made, a gate layer (2) material, a gate insulating layer (3) material and an active layer material are deposited successively. The gate layer (2), the gate insulating layer (3) and the active layer are made through one patterning process. At least one mask process is saved and the process complexity is reduced.

Abstract: An embodiment of the present application discloses a capacitive touch panel including a base substrate, on which a plurality of transparent conductive patters being capable of transmitting touch signals and not overlapping with each are provided, and each transparent conductive pattern is an integrated pattern made of a same material layer. An embodiment of the present application further provides a method for manufacturing a capacitive touch panel, which includes forming a plurality of transparent conductive patterns on a base substrate through one mask patterning process. An embodiment of the present application further includes a display device comprising the capacitive touch panel as described above. An embodiment of the present application can save masks and can manufacture capacitive touch panels at a low cost. Furthermore, the embodiments of the present application have advantages of high production efficiency and of high yield rate.

Abstract: Embodiments of the present disclosure provide a method for producing a TFT array substrate and a method for producing a display apparatus. The method for producing the TFT array substrate includes forming a semiconductor layer onto a substrate, and forming a shading pattern onto the semiconductor layer at a position at least corresponding to a channel region of the semiconductor layer, wherein the shading pattern contacts with the semiconductor layer; forming a transparent electrode of ITO material onto the substrate formed with the shading pattern, and removing the shading pattern after forming the transparent electrode.

Abstract: The embodiments of the present invention provide a thin film transistor including a gate, an upper active layer, a lower active layer, an upper source, a lower source, an upper drain and a lower drain. The upper active layer and the lower active layer are disposed at an upper side and a lower side of the gate, respectively, the lower source and the lower drain are connected to the lower active layer, respectively, and the upper source and the upper drain are connected to the upper active layer, respectively. The embodiments of the present invention also provide an array substrate including the thin film transistor, a method of fabricating the array substrate, and a display device including the array substrate.