Abstract: A liquid crystal display panel includes an array substrate and the array substrate includes: cascaded gate driver modules in the gate driver circuit area, the gate driver modules each including a first thin film transistor, the first thin film transistor including a first electrode and a second electrode, each first electrode being connected to a scan line located in the display area, and each second electrode being connected to a clock signal line; and a plurality of first spacers disposed in the gate driver circuit area. In a plan view of the liquid crystal display panel, the gate driver modules are arranged at intervals along a first direction, the first thin film transistors are arranged at intervals along the first direction, and the first spacers are located outside the second electrodes.

Abstract: The present application provides a pixel structure and a display panel. The pixel structure includes pixel units, data lines, and scan lines. The pixel unit includes a main pixel region and a sub-pixel region. Each data line includes a first data line section, a second data line section, and a third data line section. Each first data line section is arranged between the two main pixel regions of two adjacent pixel units. The second data line section and the third data line section are arranged in the two sub-pixel regions of adjacent two pixel units, respectively.

Abstract: A pixel structure and a display panel are provided. The pixel structure includes a first pixel electrode, a first longitudinal signal line, and a second longitudinal signal line. The first pixel electrode includes a first main pixel area and a first sub-pixel area. The first longitudinal signal line includes a first main line and a first secondary-line. The second longitudinal signal line includes a second main line and a second secondary-line. The first main line and the second main line are arranged in the first main pixel area, and the first secondary-line and the second secondary-line are arranged in the first sub-pixel area.

Abstract: The present application discloses an array substrate and a display panel. The array substrate includes a plurality of pixel units arranged in an array, each of the pixel units includes a thin film transistor. The thin film transistor includes a gate electrode and a drain electrode. A first overlap region and a non-overlap region is defined between the gate electrode and the drain electrode. The first overlap region is adjacent to the non-overlap region. A width of a cross section of the drain electrode in the first overlap region is less than a width of a cross section of the drain electrode in the non-overlap region. The array substrate can reduce a parasitic capacitor between the gate electrode and drain electrode.

Abstract: A display device is provided, including a circuit board, a display panel, a plurality of clock signal lines, and a plurality of grounding resistors. Each clock signal line extends from the circuit board to a non-display area of the display panel. The plurality of grounding resistors are disposed on the circuit board. Each grounding resistor is connected to a corresponding clock signal line, and is configured to reduce a voltage value of high level of the clock signal.

Abstract: Provided herein are systems and methods for enhancement of polyphenols, such as chlorogenic acids, chicoric acid, anthocyanins, and water-soluble quercetin derivatives, production in red lettuces. Also provided are transgenic lettuce for the production of polyphenols. Also provided are parts of such transgenic lettuces, such as seeds leaves, and extracts. The disclosure also provides methods of using the new lettuces and parts thereof for protection against viral/bacterial infection (i.e., by inhibiting activities of COVID-19 virus/enzymes) diabetes, cardiovascular diseases, memory and eyesight loss, inflammation, and cancer.

Abstract: The present application provides a pixel structure and a display panel. The pixel structure includes pixel units, data lines, and scan lines. The pixel unit includes a main pixel region and a sub-pixel region. Each data line includes a first data line section, a second data line section, and a third data line section. Each first data line section is arranged between the two main pixel regions of two adjacent pixel units. The second data line section and the third data line section are arranged in the two sub-pixel regions of adjacent two pixel units, respectively.

Abstract: The present application discloses an array substrate and a display panel. The array substrate includes a plurality of pixel units arranged in an array, each of the pixel units includes a thin film transistor. The thin film transistor includes a gate electrode and a drain electrode. A first overlap region and a non-overlap region is defined between the gate electrode and the drain electrode. The first overlap region is adjacent to the non-overlap region. A width of a cross section of the drain electrode in the first overlap region is less than a width of a cross section of the drain electrode in the non-overlap region. The array substrate can reduce a parasitic capacitor between the gate electrode and drain electrode.

Abstract: A pixel structure and a display panel are provided. The pixel structure includes a first pixel electrode, a first longitudinal signal line, and a second longitudinal signal line. The first pixel electrode includes a first main pixel area and a first sub-pixel area. The first longitudinal signal line includes a first main line and a first secondary-line. The second longitudinal signal line includes a second main line and a second secondary-line. The first main line and the second main line are arranged in the first main pixel area, and the first secondary-line and the second secondary-line are arranged in the first sub-pixel area.

Abstract: A display device is provided, including a circuit board, a display panel, a plurality of clock signal lines, and a plurality of grounding resistors. Each clock signal line extends from the circuit board to a non-display area of the display panel. The plurality of grounding resistors are disposed on the circuit board. Each grounding resistor is connected to a corresponding clock signal line, and is configured to reduce a voltage value of high level of the clock signal.

Abstract: A pixel unit and an LCD device are disclosed. The pixel unit comprises four sub-pixel units. Each of the sub-pixel units comprises a pixel electrode, comprising a plurality of strip portions positioned at intervals. Two adjacent strip portions define a slit. One strip portion and one slit adjacent to the strip portion are defined as an electrode portion and a width of the electrode portion is a sum of a width of the slit and a width of the strip portion. The width of each of the electrode portions and/or the width of each of the strip portions and/or the width of each of the slits is different. Since the pixel electrodes in different positions have a different aperture ratio-voltage curve. This improves the viewing angle deviation of the four domain pixel electrode.

Abstract: The present application provides a GOA device and a gate driving circuit. The GOA device includes a pull-up control circuit, a bootstrap capacitor, a pull-up circuit, a pull-down circuit, and a pull-down holding circuit. The present application decreases a number of TFTs of the gate driving circuit and simplifies a structure of the gate driving circuit by multiplexing the bootstrap capacitor, the pull-down circuit, and the pull-down holding circuit.

Abstract: A pixel unit and an LCD device are disclosed. The pixel unit comprises four sub-pixel units. Each of the sub-pixel units comprises a pixel electrode, comprising a plurality of strip portions positioned at intervals. Two adjacent strip portions define a slit. One strip portion and one slit adjacent to the strip potion are defined as an electrode portion and a width of the electrode portion is a sum of a width of the slit and a width of the strip portion. The width of each of the electrode portions and/or the width of each of the strip portions and/or the width of each of the slits is different. Since the pixel electrodes in different positions have a different aperture ratio-voltage curve. This improves the viewing angle deviation of the four domain pixel electrode.

Abstract: The present application provides a GOA device and a gate driving circuit. The GOA device includes a pull-up control circuit, a bootstrap capacitor, a pull-up circuit, a pull-down circuit, and a pull-down holding circuit. The present application decreases a number of TFTs of the gate driving circuit and simplifies a structure of the gate driving circuit by multiplexing the bootstrap capacitor, the pull-down circuit, and the pull-down holding circuit.

Abstract: The present application proposes a display panel, including a display area and a non-display area surrounding the display area, wherein the display panel includes: a plurality of metal traces and a plurality of color resist blocks located in the display area; and a test key located in the non-display area, wherein the test key includes a plurality of color resist patterns and a plurality of metal patterns, each of the color resist patterns corresponds to a corresponding one of the color resist blocks, each of the metal patterns corresponds to one of the metal traces, and each of the color resist patterns is disposed correspondingly between adjacent ones of the metal patterns.

Abstract: The present application proposes a display panel, including a display area and a non-display area surrounding the display area, wherein the display panel includes: a plurality of metal traces and a plurality of color resist blocks located in the display area; and a test key located in the non-display area, wherein the test key includes a plurality of color resist patterns and a plurality of metal patterns, each of the color resist patterns corresponds to a corresponding one of the color resist blocks, each of the metal patterns corresponds to one of the metal traces, and each of the color resist patterns is disposed correspondingly between adjacent ones of the metal patterns.

Abstract: A gate driver on array (GOA) circuit and a display panel are provided. At least one reverse unit of a nth-stage GOA unit of the GOA circuit is a first reverse unit, which includes three reverse transistors. During an operation stage, when a potential of a first node is low, an input terminal of a maintenance unit is at a high potential, and when the first node is at a high potential, the input terminal of the maintenance unit is at a low potential. Only three transistors are used to achieve that a potential of the first node is opposite to a potential of a signal at the input terminal of the maintenance unit, which saves space.

Abstract: A near space aircraft pod, including a pod body and a covering piece, where a heat dissipation part is disposed on the pod body for dissipating heat inside the pod body; and the covering piece is connected to the outside of the pod body in a movable manner, for covering the heat dissipation part or keeping a pre-designed distance from the heat dissipation part. According to the near space aircraft pod provided in the embodiments, the covering piece can adjust a distance from the heat dissipation part in time or cover the heat dissipation part based on a temperature change. Therefore, a heat dissipation speed of the pod can be effectively controlled, so that temperature inside the pod is kept in a proper range, and it is ensured that electronic devices in the pod operate under a good temperature environment.

Abstract: The present disclosure provides a GOA device and a gate drive circuit. The GOA device includes at least two GOA units in cascade. The present disclosure connects the input terminal of the pull-up control circuit to the start signal of the n?7-th stage, the control node (Qn) of the n-th GOA unit is thus pulled up to the first high potential and the bootstrap capacitor is charged. The control node (Qn) is charged 7 stages in advance, which resolves the technical problem of insufficient charging of the high-resolution high-refresh rate display panel in the related art.

Abstract: The present disclosure discloses a three-dimensional topographic mapping system and mapping method. The system includes: a floating platform, a detection apparatus, and a ground apparatus, where the floating platform is located in the stratosphere above a predetermined ground area that is to be mapped; the detection apparatus is arranged on the floating platform and configured to map the predetermined ground area according to mapping instruction information transmitted by the ground apparatus, and return mapping data to the ground apparatus; and the ground apparatus processes the returned mapping data to obtain DEM data. In the three-dimensional topographic mapping system according to embodiments of the present disclosure, the detection apparatus is arranged on the floating platform to map the predetermined ground area and cooperate with the ground apparatus to calculate the mapping data.