Abstract: The disclosure provides a battery pack, a power tool system and a charging system. The battery pack includes a battery pack housing in which a battery cell assembly and a circuit board are mounted. The circuit board is electrically connected with the battery cell assembly. A plurality of Type-C connectors are arranged on the circuit board and electrically connected to the circuit board to realize an electrical connection between the battery cell assembly and the Type-C connectors, and are configured to connect external devices.

Abstract: Semiconductor structure and its fabrication method are provided. The method includes providing a substrate, where the substrate includes a first region having a first metal structure and a second region having a second metal structure; forming a device layer on each of top surfaces of the substrate, the first metal structure and the second metal structure; forming a first through hole in the device layer at the first region, where the first through hole exposes at least a portion of surfaces of the first metal structure, and forming a second through hole in the device layer at the second region, where the second through hole passes through the first device and exposes at least a portion of surfaces of the second metal structure; and using a selective metal growth process, forming a first plug in the first through hole and forming a second plug in the second through hole.

Abstract: Semiconductor structure and its fabrication method are provided. The method includes providing a substrate, where the substrate includes a first region having a first metal structure and a second region having a second metal structure; forming a device layer on each of top surfaces of the substrate, the first metal structure and the second metal structure; forming a first through hole in the device layer at the first region, where the first through hole exposes at least a portion of surfaces of the first metal structure, and forming a second through hole in the device layer at the second region, where the second through hole passes through the first device and exposes at least a portion of surfaces of the second metal structure; and using a selective metal growth process, forming a first plug in the first through hole and forming a second plug in the second through hole.

Abstract: A method is provided for fabricating a fin field-effect transistor. The method includes providing a substrate having a first region and a second region; and forming a plurality of fin structures on a surface of the substrate. The method also includes forming a first mask layer having a plurality of first openings exposing the fin structures in the first region near the second region; and removing the fin structures in the first region near the second region. Further, the method includes forming a second mask layer on the fin structures in the second region; and removing the fin structures in the first region. Further, the method also includes forming fins by etching the substrate using the fin structures in the second region as an etching mask; and forming a gate structure and source/drain regions in the fins at both sides of the gate structure.

Abstract: A method is provided for fabricating a fin field-effect transistor. The method includes providing a substrate having a first region and a second region; and forming a plurality of fin structures on a surface of the substrate. The method also includes forming a first mask layer having a plurality of first openings exposing the fin structures in the first region near the second region; and removing the fin structures in the first region near the second region. Further, the method includes forming a second mask layer on the fin structures in the second region; and removing the fin structures in the first region. Further, the method also includes forming fins by etching the substrate using the fin structures in the second region as an etching mask; and forming a gate structure and source/drain regions in the fins at both sides of the gate structure.

Abstract: The present invention discloses a method of optimizing threshold voltage of P-type MOS transistor, including: providing a semiconductor substrate; forming a P-type MOS transistor on the semiconductor substrate; and performing a second N-type ion implantation in the source and drain extension regions. A P-type MOS transistor and a method for forming the same are also provided, the method includes: providing a semiconductor substrate including a region I and a region II being concentric with the region I and occupying 15% to 25% of the area of the whole semiconductor substrate; forming a P-type MOS transistor on the semiconductor substrate; and performing a second N-type ion implantation in the source and drain extension regions of the region II. Therefore, the reduction in threshold voltage of the P-type MOS transistors in region II of the semiconductor substrate is suppressed.