Abstract: A hot-dipped aluminum-zinc or zinc-aluminum-magnesium multiphase steel having a yield strength of greater than or equal to 450 MPa and a rapid heat-treatment hot plating manufacturing method therefor. The steel comprises the following components, in percentage by weight: 0.06-0.12% of C, 0.05-0.30% of Si, 1.0-1.8% of Mn, P?0.015%, S?0.015%, N?0.04%, Cr?0.50%, and further comprises one or both of Ti or Nb, with 0-0.045% of Nb and 0-0.045% of Ti, the balance being Fe and other unavoidable impurities. In addition, the following conditions also need to be met: 0.25?(C+Mn/6)?0.40; Mn/S?150; when no Ti is contained, Nb meets 0.01%?(Nb?0.22C?1.1N)?0.03%; when no Nb is contained, Ti meets 0.3?Ti/C?0.6; and when Ti and Nb are added in a compound mode, 0.03%?(Ti+Nb)?0.07%.

Abstract: The present disclosure provides a method for recycling urea-formaldehyde (UF) from a wood-based panel. In the present disclosure, the UF is depolymerized by an ultrasonic treatment, and depolymerized UF can be reused for UF manufacture and wood-based panel production. The recycled and treated UF can be repeatedly used in wood-based panel manufacture without affecting performances of the wood-based panel. UF-glued wood-based panels can be recycled, and a recycled wood-based panel raw material can replace at least 50% of a non-recycled wood-based raw material for particle board production without affecting performances of the wood-based panel.

Abstract: An array substrate includes a base substrate, a gate electrode, a gate insulating layer and an active layer arranged on the base substrate in a laminated way. The array substrate further includes a passivation layer, a source electrode, a drain electrode, a first electrode and a second electrode. A first via hole arranged in the passivation layer may include two sloped lateral faces arranged opposite to each other. The first electrode may at least partially cover one lateral face of the first via hole. The second electrode electrically connected to a common electrode lead may at least partially cover the other lateral face of the first via hole. The source electrode and the drain electrode may be connected to the active layer through a second via hole which is arranged in the passivation layer. The first electrode is electrically connected to the source electrode or the drain electrode.

Abstract: The present invention provides a manufacturing method of an array substrate, comprising steps of: forming a gate and a gate line on a substrate; forming a gate insulating layer on the gate and the gate line; forming a pixel electrode on the gate insulating layer; and forming a first connecting via in a portion of the gate insulating layer in a non-display region and corresponding to the gate line, wherein the first connecting via is configured to connect a scanning signal trace to the gate line.

Abstract: An array substrate according to an embodiment of the present disclosure may include a base substrate, a gate electrode, a gate insulating layer and an active layer arranged on the base substrate in a laminated way. The array substrate may further include a passivation layer arranged on the active layer, a source electrode, a drain electrode, a first electrode and a second electrode arranged on the passivation layer and on a same layer. A first via hole may be arranged in the passivation layer, and the first via hole may include two sloped lateral faces arranged opposite to each other. The first electrode may at least partially cover one lateral face of the first via hole, the second electrode may at least partially cover the other lateral face of the first via hole. The second electrode may be electrically connected to a common electrode lead. A second via hole may be further arranged in the passivation layer.

Abstract: The present invention provides a manufacturing method of an array substrate, comprising steps of: forming a gate and a gate line on a substrate; forming a gate insulating layer on the gate and the gate line; forming a pixel electrode on the gate insulating layer; and forming a first connecting via in a portion of the gate insulating layer in a non-display region and corresponding to the gate line, wherein the first connecting via is configured to connect a scanning signal trace to the gate line.