Abstract: An array substrate includes a base substrate, a gate electrode, a gate insulating layer and an active layer arranged on the base substrate in a laminated way. The array substrate further includes a passivation layer, a source electrode, a drain electrode, a first electrode and a second electrode. A first via hole arranged in the passivation layer may include two sloped lateral faces arranged opposite to each other. The first electrode may at least partially cover one lateral face of the first via hole. The second electrode electrically connected to a common electrode lead may at least partially cover the other lateral face of the first via hole. The source electrode and the drain electrode may be connected to the active layer through a second via hole which is arranged in the passivation layer. The first electrode is electrically connected to the source electrode or the drain electrode.

Abstract: The present invention provides a manufacturing method of an array substrate, comprising steps of: forming a gate and a gate line on a substrate; forming a gate insulating layer on the gate and the gate line; forming a pixel electrode on the gate insulating layer; and forming a first connecting via in a portion of the gate insulating layer in a non-display region and corresponding to the gate line, wherein the first connecting via is configured to connect a scanning signal trace to the gate line.

Abstract: An array substrate according to an embodiment of the present disclosure may include a base substrate, a gate electrode, a gate insulating layer and an active layer arranged on the base substrate in a laminated way. The array substrate may further include a passivation layer arranged on the active layer, a source electrode, a drain electrode, a first electrode and a second electrode arranged on the passivation layer and on a same layer. A first via hole may be arranged in the passivation layer, and the first via hole may include two sloped lateral faces arranged opposite to each other. The first electrode may at least partially cover one lateral face of the first via hole, the second electrode may at least partially cover the other lateral face of the first via hole. The second electrode may be electrically connected to a common electrode lead. A second via hole may be further arranged in the passivation layer.

Abstract: The present invention provides a manufacturing method of an array substrate, comprising steps of: forming a gate and a gate line on a substrate; forming a gate insulating layer on the gate and the gate line; forming a pixel electrode on the gate insulating layer; and forming a first connecting via in a portion of the gate insulating layer in a non-display region and corresponding to the gate line, wherein the first connecting via is configured to connect a scanning signal trace to the gate line.