Patents by Inventor Xiaojiang Yu

Xiaojiang Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10838122
    Abstract: A color filter substrate and the fabricating method are provided. The color filter substrate comprises of the following elements. A glass substrate and a black matrix formed thereon. The black matrix includes a first ring protrusion on an edge thereof. Color resists, a planar layer and a photoresist spacer are disposed in sequence on the glass substrate. The planar layer includes a second ring protrusion formed thereon corresponding to a location of the first ring protrusion. A projection of the photoresist spacer on the glass substrate is inside the first ring protrusion and the second ring protrusion. A polyimide film is coated on the planar layer and the photoresist spacer. The second ring protrusions can block the backflow of the polyimide solution on the photoresist spacer, for reducing the halo area of polyimide film, increasing the open ratio of the panel and promoting the performance of the LTPS display.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: November 17, 2020
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Xiaojiang Yu
  • Patent number: 10768456
    Abstract: A low temperature poly-silicon (LTPS) display panel and a liquid crystal display device include a color filter substrate, an array substrate, and a frame sealing glue. The array substrate includes a glass substrate, a functional structure layer, and a third inorganic dielectric layer. The third inorganic dielectric layer connects with the frame sealing glue, and at least a row of first anti-crack holes are formed on the third inorganic dielectric layer adjacent to the frame sealing glue. The at least a row of first anti-crack holes include a plurality of the first anti-crack holes arranged in a direction along and in parallel with the frame sealing glue.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: September 8, 2020
    Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd.
    Inventor: Xiaojiang Yu
  • Publication number: 20200233126
    Abstract: A color filter substrate and the fabricating method are provided. The color filter substrate comprises of the following elements. A glass substrate and a black matrix formed thereon. The black matrix includes a first ring protrusion on an edge thereof. Color resists, a planar layer and a photoresist spacer are disposed in sequence on the glass substrate, The planar layer includes a second ring protrusion formed thereon corresponding to a location of the first ring protrusion. A projection of the photoresist spacer on the glass substrate is inside the first ring protrusion and the second ring protrusion. A polyimide film is coated on the planar layer and the photoresist spacer. The second ring protrusions can block the backflow of the polyimide solution on the photoresist spacer, for reducing the halo area of polyimide film, increasing the open ratio of the panel and promoting the performance of the LTPS display.
    Type: Application
    Filed: October 26, 2017
    Publication date: July 23, 2020
    Inventor: Xiaojiang YU
  • Patent number: 10600811
    Abstract: The invention provides a TFT array substrate and LCD panel. The TFT array substrate adopts a Notch design, with a base substrate disposed with a groove at one end. The base substrate comprises a functional area and a peripheral area located outside the functional area, and the planarization layer on the base substrate has a first portion corresponding to the functional area, wherein the first portion adjacent to the groove is provided with at least one pit, and the depth of the pit is smaller than the thickness of the first portion. When the TFT array substrate and the CF substrate are assembled, after the LC is injected between TFT array substrate and CF substrate, the LC accumulation generated in the first portion of the planarization layer near the groove during diffusion is in the pit, thereby making the LC layer thickness uniform and improved quality of LCD panel.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: March 24, 2020
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Ling Gao, Xiaojiang Yu
  • Publication number: 20200081279
    Abstract: A low temperature poly-silicon (LTPS) display panel and a liquid crystal display device include a color filter substrate, an array substrate, and a frame sealing glue. The array substrate includes a glass substrate, a functional structure layer, and a third inorganic dielectric layer. The third inorganic dielectric layer connects with the frame sealing glue, and at least a row of first anti-crack holes are formed on the third inorganic dielectric layer adjacent to the frame sealing glue. The at least a row of first anti-crack holes include a plurality of the first anti-crack holes arranged in a direction along and in parallel with the frame sealing glue.
    Type: Application
    Filed: August 2, 2018
    Publication date: March 12, 2020
    Applicant: Wuhan China Star Optoelectronics Technology Co., Ltd.
    Inventor: Xiaojiang YU
  • Patent number: 10522565
    Abstract: An array substrate provided comprises a gate insulating layer, touch control element and first conducting wire disposed on a substrate; insulating interlayer covering gate insulating layer, touch control element and first conducting wire; protective wire arranged along the surface periphery of insulating interlayer; planarization layer covering insulating interlayer and protective wire, and second conducting wire disposed on surface of planarization layer; wherein touch control element is insulated from first conducting wire comprising an extension section, and free end of extension section is a first end; protective wire is electrically connected with first end; second conducting wire comprises a second and third end arranged oppositely and a contact position between second and third end; second end is electrically connected with touch control element, and contact position is electrically connected with a portion of first conducting wire inner substrate.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: December 31, 2019
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Chuan Wang, Meng Zhou, Xiaojiang Yu
  • Publication number: 20190326331
    Abstract: The invention provides a TFT array substrate and LCD panel. The TFT array substrate adopts a Notch design, with a base substrate disposed with a groove at one end. The base substrate comprises a functional area and a peripheral area located outside the functional area, and the planarization layer on the base substrate has a first portion corresponding to the functional area, wherein the first portion adjacent to the groove is provided with at least one pit, and the depth of the pit is smaller than the thickness of the first portion. When the TFT array substrate and the CF substrate are assembled, after the LC is injected between TFT array substrate and CF substrate, the LC accumulation generated in the first portion of the planarization layer near the groove during diffusion is in the pit, thereby making the LC layer thickness uniform and improved quality of LCD panel.
    Type: Application
    Filed: September 19, 2018
    Publication date: October 24, 2019
    Inventors: Ling Gao, Xiaojiang Yu
  • Publication number: 20190267405
    Abstract: An array substrate provided comprises a gate insulating layer, touch control element and first conducting wire disposed on a substrate; insulating interlayer covering gate insulating layer, touch control element and first conducting wire; protective wire arranged along the surface periphery of insulating interlayer; planarization layer covering insulating interlayer and protective wire, and second conducting wire disposed on surface of planarization layer; wherein touch control element is insulated from first conducting wire comprising an extension section, and free end of extension section is a first end; protective wire is electrically connected with first end; second conducting wire comprises a second and third end arranged oppositely and a contact position between second and third end; second end is electrically connected with touch control element, and contact position is electrically connected with a portion of first conducting wire inner substrate.
    Type: Application
    Filed: July 25, 2018
    Publication date: August 29, 2019
    Inventors: Chuan WANG, Meng ZHOU, Xiaojiang YU
  • Publication number: 20180301532
    Abstract: Disclosed is a thin film transistor, which includes a shading layer and a poly-silicon layer, the shading layer being arranged below the poly-silicon layer. when viewed from a top perspective, the shading layer and the poly-silicon layer have an angle therebetween, the angle being an acute angle or an obtuse angle. The thin film transistor breaks processing constrains and makes it possible to reduce the inclination degree of the poly-silicon layer at an edge of a sloping part of the shading layer in a larger range, thereby improving the conductivity of the poly-silicon layer.
    Type: Application
    Filed: March 9, 2017
    Publication date: October 18, 2018
    Applicant: Wuhan China Star Optoelectronics Technology Co., L td.
    Inventors: Yuebai Han, Xiaojiang Yu
  • Publication number: 20180292719
    Abstract: Disclosed is an array substrate and a liquid crystal display panel including the array substrate. The array substrate includes: a dummy pixel region, a display region, and a drive circuit region, wherein the dummy pixel region is located between the display region and the drive circuit region, both of the display region and the dummy pixel region being provided with a plurality of poly-silicon wires and a plurality of gate lines, the poly-silicon wires and the gate lines crossing each other in different layers. An overlapping area between the poly-silicon wires and the gate lines in the dummy pixel region is larger than an overlapping area between the poly-silicon wires and the gate lines in the display region. The array substrate is capable of effectively discharging an electrostatic voltage and significantly weakening the electrostatic voltage that may continue to be introduced into the display region along the gate lines, so as to prevent damage to the function of pixels in the display region.
    Type: Application
    Filed: March 14, 2017
    Publication date: October 11, 2018
    Inventor: Xiaojiang YU
  • Patent number: 9971214
    Abstract: A manufacturing method of an array substrate structure is disclosed, in which after a common electrode is formed, a reduction resistant layer is first formed on the common electrode before deposition of a second insulation layer in order to prevent the film quality of the common electrode from being affected by a reductive atmosphere generated in a process of directly depositing the second insulation layer on the common electrode thereby reducing the influence on the transmittal of the common electrode caused by the deposition of the second insulation layer on the common electrode and providing the common electrode with increased transmittal and enhancing displaying performance.
    Type: Grant
    Filed: September 4, 2017
    Date of Patent: May 15, 2018
    Assignees: SHENZHEN CHINA STAR OPTOELECTRONIC TECHNOLOGY CO., LTD., WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Xiaojiang Yu, Haibo Du
  • Patent number: 9946108
    Abstract: The present invention provides a display panel and a manufacture method thereof. By locating the matrix electrode corresponding to the black matrix on one side of the color film substrate, which is close to the liquid crystal layer, and because the matrix electrode is coupled to the common electrode signal, no voltage difference exists between the matrix electrode and the common electrode, and no matter in condition of being electrified or not electrified, the liquid crystal layer between the matrix electrode and the common electrode of the array substrate is not orientated and constantly appears in an opaque state so that no interference generates to light between adjacent pixels of the panel to eliminate the large view angle color washout of the panel and to improve the display quality of the LTPS display panel.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: April 17, 2018
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Xiaojiang Yu
  • Patent number: 9934749
    Abstract: A complementary gate driver on array circuit employed for panel display includes a plurality of GOA units that are cascade connected, in which an nth GOA unit controls charge to an nth horizontal scanning line G(n) in a display area and includes a pull-up circuit module, a pull-down circuit module, a pull-down holding circuit module, a pull-up controlling circuit module, a pull-down circuit module of an nth gate signal point Q(n), and a bootstrap capacitor. The pull-up circuit module, the pull-down circuit module, the pull-down holding circuit module, the pull-down circuit module of the nth gate signal point Q(n), and the bootstrap capacitor are respectively coupled to the nth gate signal point Q(n) and the nth horizontal scanning line G(n), and the pull-up controlling circuit module is coupled to the nth horizontal scanning line G(n).
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: April 3, 2018
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd.
    Inventor: Xiaojiang Yu
  • Publication number: 20180069099
    Abstract: The present invention provides a manufacture method of a N type thin film transistor. In the manufacture process, the chemical solution is employed to etch the channel region of the N type thin film transistor to raise a surface roughness of the low temperature polysilicon in the channel region of the N type thin film transistor, and thus to raise the surface defect density of the low temperature polysilicon in the channel region of the N type thin film transistor. Then, the threshold voltage of the manufactured N type thin film transistor moves toward the positive direction to ensure that the manufactured N type thin film transistor can be closed in time under the low voltage. The production efficiency is high and the production cost is low.
    Type: Application
    Filed: May 26, 2016
    Publication date: March 8, 2018
    Inventor: Xiaojiang Yu
  • Publication number: 20180067367
    Abstract: The present invention provides a LTPS display panel and a manufacture method thereof. In the LTPS display panel, the edge of the back matrix (12) comprises a convex part (104) capable of ensuring that the light emitted from the pixel unit (22) of the array substrate (20) only penetrates through the color resist block (131/132/133) corresponding to the pixel unit (22) in the color film substrate (10), and no light leakage happens between adjacent pixel units and thus, can reduce the large view angle color washout to improve the display quality of the LTPS display panel. In the manufacture method of the LTPS display panel, one halftone mask process is employed to form the black matrix (12), and the edge of the back matrix (12) comprises a convex part (104) which can better shade the light leakage between adjacent pixel units as watching in the large view angle.
    Type: Application
    Filed: May 26, 2016
    Publication date: March 8, 2018
    Inventors: Xiaojiang Yu, Wenzhi Le, Zhiyuan Shen
  • Publication number: 20180011370
    Abstract: The present invention provides a display panel and a manufacture method thereof. By locating the matrix electrode corresponding to the black matrix on one side of the color film substrate, which is close to the liquid crystal layer, and because the matrix electrode is coupled to the common electrode signal, no voltage difference exists between the matrix electrode and the common electrode, and no matter in condition of being electrified or not electrified, the liquid crystal layer between the matrix electrode and the common electrode of the array substrate is not orientated and constantly appears in an opaque state so that no interference generates to light between adjacent pixels of the panel to eliminate the large view angle color washout of the panel and to improve the display quality of the LTPS display panel.
    Type: Application
    Filed: May 26, 2016
    Publication date: January 11, 2018
    Inventor: Xiaojiang YU
  • Publication number: 20170363902
    Abstract: A manufacturing method of an array substrate structure is disclosed, in which after a common electrode is formed, a reduction resistant layer is first formed on the common electrode before deposition of a second insulation layer in order to prevent the film quality of the common electrode from being affected by a reductive atmosphere generated in a process of directly depositing the second insulation layer on the common electrode thereby reducing the influence on the transmittal of the common electrode caused by the deposition of the second insulation layer on the common electrode and providing the common electrode with increased transmittal and enhancing displaying performance.
    Type: Application
    Filed: September 4, 2017
    Publication date: December 21, 2017
    Inventors: Xiaojiang Yu, Haibo Du
  • Patent number: 9785023
    Abstract: The present invention provides an array substrate structure and a manufacturing method thereof, in which after a common electrode (91) is formed, a reduction resistant layer (82) is first formed on the common electrode (91) before deposition of a second insulation layer (83) in order to prevent the film quality of the common electrode (91) from being affected by a reductive atmosphere generated in a process of directly depositing the second insulation layer (83) on the common electrode (91) thereby reducing the influence on the transmittal of the common electrode (91) caused by the deposition of the second insulation layer (83) on the common electrode (91) and providing the common electrode (91) with increased transmittal and enhancing displaying performance.
    Type: Grant
    Filed: May 25, 2015
    Date of Patent: October 10, 2017
    Assignees: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD., WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Xiaojiang Yu, Haibo Du
  • Patent number: 9779681
    Abstract: The present invention discloses a shift register unit, employed for providing a gate voltage to a nth pixel of a liquid crystal display, and comprising first to third P-type transistors, and gates of the first, second P-type transistors respectively receive gate voltages of n?2th, n?2th pixels, and first end of the first, second P-type transistors respectively receive first and second input signals, and both second ends of the first and second P-type transistors are coupled to a gate of the third P-type transistor; the gate voltages of the n?2th, n?2th pixels are respectively employed to control on-off of the first and second P-type transistors, and to make the first input signal on-off the third P-type transistor; n is a nature number larger than 2; a first end of the third P-type transistor is coupled to a first clock signal or a second clock signal, and a second end is employed as being a voltage output end to be coupled to the nth pixel.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: October 3, 2017
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd.
    Inventors: Xiaojiang Yu, Xin Zhang, Jun Xia
  • Publication number: 20170270886
    Abstract: A complementary gate driver on array circuit employed for panel display includes a plurality of GOA units that are cascade connected, in which an nth GOA unit controls charge to an nth horizontal scanning line G(n) in a display area and includes a pull-up circuit module, a pull-down circuit module, a pull-down holding circuit module, a pull-up controlling circuit module, a pull-down circuit module of an nth gate signal point Q(n), and a bootstrap capacitor. The pull-up circuit module, the pull-down circuit module, the pull-down holding circuit module, the pull-down circuit module of the nth gate signal point Q(n), and the bootstrap capacitor are respectively coupled to the nth gate signal point Q(n) and the nth horizontal scanning line G(n), and the pull-up controlling circuit module is coupled to the nth horizontal scanning line G(n).
    Type: Application
    Filed: June 8, 2017
    Publication date: September 21, 2017
    Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd.
    Inventor: Xiaojiang YU