Patents by Inventor Xiaojie (Warren) He

Xiaojie (Warren) He has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6653860
    Abstract: An improved, high density CPLD includes a plurality of macrocell sections. Each macrocell section can receive a relatively large number of independent input terms and can generate as a base cluster, at least as many as 5 different product term signals (PT's) therefrom. Part or all of the macrocell's local 5 PT's may be used for generating a local sum-of-products (SoP) signal in a local, first-level ORring operation. Additionally SoP's generated in neighboring macrocell sections may be selectively and incrementally cascaded (cross-laced) for supplemental summing into the local SoP signal. SoP signals of neighboring sections may be further selected in a sums sharing array for second level summing. The combination of the first-level cascading (cross-lacing) and second-level sums sharing provides a wide range of programmably selectable granulations including that of having relatively fast generation of a sum of just a few PT's (e.g.
    Type: Grant
    Filed: August 10, 2001
    Date of Patent: November 25, 2003
    Assignee: Lattice Semiconductor Corporation
    Inventors: Om P. Agrawal, Xiaojie (Warren) He, Claudia A. Stanley, Larry R. Metzger, Chong M. Lee
  • Publication number: 20030107401
    Abstract: An improved, high density CPLD includes a plurality of macrocell sections. Each macrocell section can receive a relatively large number of independent input terms and can generate as a base cluster, at least as many as 5 different product term signals (PT's) therefrom. Part or all of the macrocell's local 5 PT's may be used for generating a local sum-of-products (SoP) signal in a local, first-level ORring operation. Additionally SoP's generated in neighboring macrocell sections may be selectively and incrementally cascaded (cross-laced) for supplemental summing into the local SoP signal. SoP signals of neighboring sections may be further selected in a sums sharing array for second level summing. The combination of the first-level cascading (cross-lacing) and second-level sums sharing provides a wide range of programmably selectable granulations including that of having relatively fast generation of a sum of just a few PT's (e.g.
    Type: Application
    Filed: August 10, 2001
    Publication date: June 12, 2003
    Applicant: LATTICE SEMICONDUCTOR CORPORATION
    Inventors: Om P. Agrawal, Xiaojie (Warren) He, Claudia A. Stanley, Larry R. Metzger, Chong M. Lee
  • Patent number: 6348813
    Abstract: An improved, scalable CPLD device has a two-tiered hierarchical switch construct comprised of a Global Switch Matrix (GSM) and an even number of Segment Switch Matrices (SSM's). An even number of Super Logic Blocks (SLB's) are coupled to each SSM. Each SSM and its SLB's define a segment that couples to the GSM. Each SLB has a relatively large number of inputs (at least 80) and can generate product term signals (PT's) that are products of independent input terms provided from the SSM to the SLB inputs. Some of the product terms generated within each SLB are dedicated to SLB-local controls. Each SLB has at least 32 macrocells and at least 16 I/O pads which feedback to both to the local SSM and the global GSM. 100% intra-segment connectivity is assured within each segment so that each segment can function as an independent, mini-CPLD. Each SSM has additional lines, dedicated for inter-segment (global) communications.
    Type: Grant
    Filed: November 22, 2000
    Date of Patent: February 19, 2002
    Assignee: Lattice Semiconductor Corporation
    Inventors: Om P. Agrawal, Claudia A. Stanley, Xiaojie (Warren) He, Larry R. Metzger, Robert A. Simon, Kerry A. Ilgenstein
  • Patent number: 6184713
    Abstract: An improved, scalable CPLD device has a two-tiered hierarchical switch construct comprised of a Global Switch Matrix (GSM) and an even number of Segment Switch Matrices (SSM's). An even number of Super Logic Blocks (SLB's) are coupled to each SSM. Each SSM and its SLB's define a segment that couples to the GSM. Each SLB has a relatively large number of inputs (at least 80) and can generate product term signals (PT's) that are products of independent input terms provided from the SSM to the SLB inputs. Some of the product terms generated within each SLB are dedicated to SLB-local controls. Each SLB has at least 32 macrocells and at least 16 I/O pads which feedback to both to the local SSM and the global GSM. 100% intra-segment connectivity is assured within each segment so that each segment can function as an independent, mini-CPLD. Each SSM has additional lines, dedicated for inter-segment (global) communications.
    Type: Grant
    Filed: June 6, 1999
    Date of Patent: February 6, 2001
    Assignee: Lattice Semiconductor Corporation
    Inventors: Om P. Agrawal, Claudia A. Stanley, Xiaojie (Warren) He, Larry R. Metzger, Robert A. Simon, Kerry A. Ilgenstein
  • Patent number: 6150841
    Abstract: An improved CPLD includes a plurality of macrocell modules (MM's) where each MM can receive a relatively large number of independent inputs (at least 80) and can generate at least 5 different product term signals (PT's) therefrom. All 5 PT's may be used for generating a local sum-of-products (SoP). Any of the 5 PT's may be stolen (steered-away) to instead provide a local control for its macrocell module. Each module includes a local SoS-producing gate that can produce a sums-of-sums signal (SoS) that represents a Boolean sum of one or more of the local SoP signal, of SoP signals of neighboring macrocell modules, and of SoS signals of neighboring macrocell modules. Simple allocation and super-allocation may be used to produce sums-of-sums signals of relatively large, one-pass function depth, such as 160PT's in one pass.
    Type: Grant
    Filed: June 6, 1999
    Date of Patent: November 21, 2000
    Assignee: Lattice Semiconductor Corporation
    Inventors: Om P. Agrawal, Claudia A. Stanley, Xiaojie (Warren) He, Chong M. Lee, Robert M. Balzli, Jr., Larry R. Metzger, Kerry A. Ilgenstein