Patents by Inventor Xiaojie Xue

Xiaojie Xue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11968646
    Abstract: Wireless communications systems and methods related to communicating control information are provided. A method of wireless communication performed by a user equipment (UE) may include sensing an interference level of at least one frequency, selecting, based on the interference level, a frequency, and communicating sidelink control information (SCI) in the selected frequency.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: April 23, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Yisheng Xue, Xiaojie Wang, Jing Sun, Chih-Hao Liu, Xiaoxia Zhang
  • Patent number: 11950222
    Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may receive a configuration that indicates multiple time intervals corresponding to multiple physical sidelink shared channels (PSSCHs) within a slot, wherein at least one PSSCH, of the multiple PSSCHs, starts in a symbol other than an initial data symbol of the slot. The UE may communicate in one or more PSSCHs, of the multiple PSSCHs, within the slot based at least in part on the configuration. Numerous other aspects are described.
    Type: Grant
    Filed: June 1, 2021
    Date of Patent: April 2, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Chih-Hao Liu, Yisheng Xue, Jing Sun, Xiaoxia Zhang, Tao Luo, Sony Akkarakaran, Xiaojie Wang, Lik Hang Silas Fong, Piyush Gupta
  • Patent number: 10490510
    Abstract: An integrated device package is disclosed. The package can include a package substrate comprising a composite die pad having an upper surface and a lower surface spaced from the upper surface along a vertical direction. The composite die pad can include an insulator die pad and a metal die pad. The insulator die pad and the metal die pad can be disposed adjacent one another along the vertical direction. The substrate can include a plurality of leads disposed about at least a portion of a perimeter of the composite die pad. An integrated device die can be mounted on the upper surface of the composite die pad.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: November 26, 2019
    Assignee: ANALOG DEVICES, INC.
    Inventors: Xiaojie Xue, Dipak Sengupta
  • Patent number: 10287161
    Abstract: An integrated device package is disclosed. The package can include a carrier, such as first integrated device die, and a second integrated device die stacked on the first integrated device die. The package can include a buffer layer which coats at least a portion of an exterior surface of the first integrated device die and which is disposed between the second integrated device die and the first integrated device die. The buffer layer can comprise a pattern to reduce transmission of stresses between the first integrated device die and the second integrated device die.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: May 14, 2019
    Assignee: ANALOG DEVICES, INC.
    Inventors: Xiaojie Xue, Michael J. Zylinski, Thomas M. Goida, Kathleen O. O'Donnell
  • Publication number: 20180047675
    Abstract: An integrated device package is disclosed. The package can include a package substrate comprising a composite die pad having an upper surface and a lower surface spaced from the upper surface along a vertical direction. The composite die pad can include an insulator die pad and a metal die pad. The insulator die pad and the metal die pad can be disposed adjacent one another along the vertical direction. The substrate can include a plurality of leads disposed about at least a portion of a perimeter of the composite die pad. An integrated device die can be mounted on the upper surface of the composite die pad.
    Type: Application
    Filed: August 7, 2017
    Publication date: February 15, 2018
    Inventors: Xiaojie Xue, Dipak Sengupta
  • Patent number: 9728510
    Abstract: An integrated device package is disclosed. The package can include a package substrate comprising a composite die pad having an upper surface and a lower surface spaced from the upper surface along a vertical direction. The composite die pad can include an insulator die pad and a metal die pad. The insulator die pad and the metal die pad can be disposed adjacent one another along the vertical direction. The substrate can include a plurality of leads disposed about at least a portion of a perimeter of the composite die pad. An integrated device die can be mounted on the upper surface of the composite die pad.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: August 8, 2017
    Assignee: ANALOG DEVICES, INC.
    Inventors: Xiaojie Xue, Dipak Sengupta
  • Patent number: 9698127
    Abstract: An integrated device die and package is disclosed. The integrated device die includes a unitary body. The unitary body can have an upper portion comprising one or more active components. The upper portion can have first and second opposing lateral sides defining at least a portion of a periphery of the upper portion such that an upper surface of the upper portion is disposed between upper edges of the first and second opposing lateral sides. The unitary body can also have a lower portion monolithically formed with the upper portion. The lower portion can comprise a pedestal extending downwardly from the upper portion. The pedestal can be laterally inset from lower edges of the first and second opposing lateral sides. The pedestal can include a distal end portion configured to couple to a carrier.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: July 4, 2017
    Assignee: ANALOG DEVICES, INC.
    Inventors: Thomas M. Goida, Xiaojie Xue
  • Publication number: 20170022051
    Abstract: An integrated device package is disclosed. The package can include a carrier, such as first integrated device die, and a second integrated device die stacked on the first integrated device die. The package can include a buffer layer which coats at least a portion of an exterior surface of the first integrated device die and which is disposed between the second integrated device die and the first integrated device die. The buffer layer can comprise a pattern to reduce transmission of stresses between the first integrated device die and the second integrated device die.
    Type: Application
    Filed: April 6, 2016
    Publication date: January 26, 2017
    Inventors: Xiaojie Xue, Michael J. Zylinski, Thomas M. Goida, Kathleen O. O'Donnell
  • Publication number: 20160336297
    Abstract: An integrated device die and package is disclosed. The integrated device die includes a unitary body. The unitary body can have an upper portion comprising one or more active components. The upper portion can have first and second opposing lateral sides defining at least a portion of a periphery of the upper portion such that an upper surface of the upper portion is disposed between upper edges of the first and second opposing lateral sides. The unitary body can also have a lower portion monolithically formed with the upper portion. The lower portion can comprise a pedestal extending downwardly from the upper portion. The pedestal can be laterally inset from lower edges of the first and second opposing lateral sides. The pedestal can include a distal end portion configured to couple to a carrier.
    Type: Application
    Filed: May 13, 2016
    Publication date: November 17, 2016
    Inventors: Thomas M. Goida, Xiaojie Xue
  • Publication number: 20160300781
    Abstract: An integrated device package is disclosed. The package can include a package substrate comprising a composite die pad having an upper surface and a lower surface spaced from the upper surface along a vertical direction. The composite die pad can include an insulator die pad and a metal die pad. The insulator die pad and the metal die pad can be disposed adjacent one another along the vertical direction. The substrate can include a plurality of leads disposed about at least a portion of a perimeter of the composite die pad. An integrated device die can be mounted on the upper surface of the composite die pad.
    Type: Application
    Filed: November 25, 2015
    Publication date: October 13, 2016
    Inventors: Xiaojie Xue, Dipak Sengupta
  • Patent number: 9343367
    Abstract: An integrated device die and package is disclosed. The integrated device die includes a unitary body. The unitary body can have an upper portion comprising one or more active components. The upper portion can have first and second opposing lateral sides defining at least a portion of a periphery of the upper portion such that an upper surface of the upper portion is disposed between upper edges of the first and second opposing lateral sides. The unitary body can also have a lower portion monolithically formed with the upper portion. The lower portion can comprise a pedestal extending downwardly from the upper portion. The pedestal can be laterally inset from lower edges of the first and second opposing lateral sides. The pedestal can include a distal end portion configured to couple to a carrier.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: May 17, 2016
    Assignee: ANALOG DEVICES, INC.
    Inventors: Thomas M. Goida, Xiaojie Xue
  • Patent number: 9278851
    Abstract: Vertical mount packages and methods for making the same are disclosed. A method for manufacturing a vertical mount package includes providing a device substrate with a plurality of device regions on a front surface, and a plurality of through-wafer vias. MEMS devices or integrated circuits are formed or mounted onto the device regions. A capping substrate having recesses is mounted over the device substrate, enclosing the device regions within cavities defined by the recesses. A plurality of aligned through-wafer contacts extend through the capping substrate and the device substrate. The device substrate and capping substrate can be singulated by cutting through the aligned through-wafer contacts, with the severed through-wafer contacts forming vertical mount leads. A vertical mount package includes a device sealed between a device substrate and a capping substrate. At least of the side edges of the package includes exposed conductive elements for vertical mount leads.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: March 8, 2016
    Assignee: ANALOG DEVICES, INC.
    Inventor: Xiaojie Xue
  • Patent number: 9209121
    Abstract: Various embodiments of an integrated device package are disclosed herein. The package may include a leadframe having a first side and a second side opposite the first side. The leadframe can include a plurality of leads surrounding a die mounting region. A first package lid may be mounted on the first side of the leadframe to form a first cavity, and a first integrated device die may be mounted on the first side of the leadframe within the first cavity. A second integrated device die can be mounted on the second side of the leadframe. At least one lead of the plurality of leads can provide electrical communication between the first integrated device die and the second integrated device die.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: December 8, 2015
    Assignee: ANALOG DEVICES, INC.
    Inventors: Thomas M. Goida, Xiaojie Xue
  • Publication number: 20150181697
    Abstract: An integrated device die and package is disclosed. The integrated device die includes a unitary body. The unitary body can have an upper portion comprising one or more active components. The upper portion can have first and second opposing lateral sides defining at least a portion of a periphery of the upper portion such that an upper surface of the upper portion is disposed between upper edges of the first and second opposing lateral sides. The unitary body can also have a lower portion monolithically formed with the upper portion. The lower portion can comprise a pedestal extending downwardly from the upper portion. The pedestal can be laterally inset from lower edges of the first and second opposing lateral sides. The pedestal can include a distal end portion configured to couple to a carrier.
    Type: Application
    Filed: December 19, 2014
    Publication date: June 25, 2015
    Inventors: Thomas M. Goida, Xiaojie Xue
  • Publication number: 20140374854
    Abstract: Vertical mount packages and methods for making the same are disclosed. A method for manufacturing a vertical mount package includes providing a device substrate with a plurality of device regions on a front surface, and a plurality of through-wafer vias. MEMS devices or integrated circuits are formed or mounted onto the device regions. A capping substrate having recesses is mounted over the device substrate, enclosing the device regions within cavities defined by the recesses. A plurality of aligned through-wafer contacts extend through the capping substrate and the device substrate. The device substrate and capping substrate can be singulated by cutting through the aligned through-wafer contacts, with the severed through-wafer contacts forming vertical mount leads. A vertical mount package includes a device sealed between a device substrate and a capping substrate. At least of the side edges of the package includes exposed conductive elements for vertical mount leads.
    Type: Application
    Filed: September 11, 2014
    Publication date: December 25, 2014
    Inventor: Xiaojie Xue
  • Patent number: 8853839
    Abstract: A housing for integrated devices that includes an air-release mechanism is disclosed. This is achieved, in various embodiments, by forming a vent hole in a package substrate, and arranging a package lid over the package substrate. The vent hole allows air to be released from within the cavity package, thereby ensuring that the package lid remains stably affixed to the package substrate despite increased temperatures during processing. The vent hole may be sealed upon mounting the package onto a mounting substrate.
    Type: Grant
    Filed: October 4, 2012
    Date of Patent: October 7, 2014
    Assignee: Analog Devices, Inc.
    Inventors: Jia Gao, Jicheng Yang, Shafi Saiyed, Siu Lung Ng, Xiaojie Xue
  • Patent number: 8836132
    Abstract: Vertical mount packages and methods for making the same are disclosed. A method for manufacturing a vertical mount package includes providing a device substrate with a plurality of device regions on a front surface, and a plurality of through-wafer vias. MEMS devices or integrated circuits are formed or mounted onto the device regions. A capping substrate having recesses is mounted over the device substrate, enclosing the device regions within cavities defined by the recesses. A plurality of aligned through-wafer contacts extend through the capping substrate and the device substrate. The device substrate and capping substrate can be singulated by cutting through the aligned through-wafer contacts, with the severed through-wafer contacts forming vertical mount leads. A vertical mount package includes a device sealed between a device substrate and a capping substrate. At least of the side edges of the package includes exposed conductive elements for vertical mount leads.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: September 16, 2014
    Assignee: Analog Devices, Inc.
    Inventor: Xiaojie Xue
  • Publication number: 20140217566
    Abstract: Various embodiments of an integrated device package are disclosed herein. The package may include a leadframe having a first side and a second side opposite the first side. The leadframe can include a plurality of leads surrounding a die mounting region. A first package lid may be mounted on the first side of the leadframe to form a first cavity, and a first integrated device die may be mounted on the first side of the leadframe within the first cavity. A second integrated device die can be mounted on the second side of the leadframe. At least one lead of the plurality of leads can provide electrical communication between the first integrated device die and the second integrated device die.
    Type: Application
    Filed: February 1, 2013
    Publication date: August 7, 2014
    Applicant: ANALOG DEVICES, INC.
    Inventors: Thomas M. Goida, Xiaojie Xue
  • Patent number: 8692366
    Abstract: A MEMS package includes a substrate having an L-shaped cross-section. The substrate includes a vertical portion having a front surface and a back surface, and a horizontal portion protruding from a lower part of the front surface of the vertical portion, wherein the front surface of the vertical portion includes a mounting region. A MEMS die is mounted on the mounting region such that the MEMS die is oriented substantially parallel to the front surface; a lid attached to the front surface of the substrate while covering the MEMS die; and a plurality of leads formed on a bottom surface of the substrate. The leads can extend substantially parallel to one another, and substantially perpendicular to the front surface. The MEMS die can be oriented substantially perpendicular to a PCB substrate on which the package is mounted.
    Type: Grant
    Filed: April 12, 2011
    Date of Patent: April 8, 2014
    Assignee: Analog Device, Inc.
    Inventors: Xiaojie Xue, Carl Raleigh
  • Patent number: 8624380
    Abstract: A vertical mount pre-molded type package for use with a MEMS sensor may be formed with a low moisture permeable molding material that surrounds a portion of the leadframes and forms a cavity in which one or multiple dies may be held. The package includes structures to reduce package vibration, reduce die stress, increase vertical mount stability, and improve solder joint reliability. The vertical mount package includes a first leadframe having first leads and molding material substantially surrounding at least a portion of the first leads. The molding material forms a cavity for holding the MEMS sensor and forms a package mounting plane for mounting the package on a base. The cavity has a die mounting plane that is substantially non-parallel to the package mounting plane. The first leads are configured to provide electrical contacts within the cavity and to provide electrical contacts to the base.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: January 7, 2014
    Assignee: Analog Devices, Inc.
    Inventors: Xiaojie Xue, Carl Raleigh, Thomas M. Goida