Abstract: This disclosure relates generally to wireless communications and, more particularly, to systems and methods for determining round trip time and layer 2 (e.g., data link) buffer size in non terrestrial networks. In one embodiment, a method performed by a communication node includes: sending a capability request message to a communication device, wherein the communication node communicates from a satellite in orbit; receiving capability information from the communication device in response to the capability request message; and determining a data link buffer size associated with communications between the communication node and the communication device based on the capability information.

Abstract: A semiconductor memory device includes a semiconductor substrate, a select gate on the semiconductor substrate, a control gate disposed adjacent to the select gate and having a first sidewall and a second sidewall, and a charge storage layer between the control gate and the semiconductor substrate. The control gate includes a third sidewall close to the second sidewall of the select gate, a fourth sidewall opposite to the third sidewall, and a non-planar top surface between the third sidewall and the fourth sidewall. The non-planar top surface includes a first surface region that descends from the third sidewall to the fourth sidewall. The charge storage layer extends to the second sidewall of the select gate.

Abstract: The disclosure relates to a method for measuring parameters of roadway low-position lighting fixtures, comprising: selecting a plurality of sets of low-position lighting fixtures with preset color temperatures and color rendering indexes, or a set of low-position lighting fixtures configurable with multiple pairs of preset color temperature and color rendering index; for each set of the plurality of sets of low-position lighting fixtures or each pair of preset color temperature and color rendering index in the set of low-position lighting fixtures, dynamically recognizing a target under different predetermined luminance levels at different predetermined operating speeds; using obtained samples to fit a relationship model between recognition distance and luminance; and based on the fitted relationship model, determining at least one set of said plurality of sets of low-position lighting fixtures or determining at least one pair of preset color temperature and color rendering index for said set of low-position

Abstract: A method for forming a semiconductor memory device is disclosed. A substrate is provided. A source diffusion region is formed in the substrate. Two floating gates are on opposite sides of the source diffusion region. A first dielectric cap layer is formed directly on each of the floating gates. An erase gate is formed on the source diffusion region. The erase gate partially overlaps an upper inner corner of each of the floating gates. A second dielectric cap layer is formed on the erase gate and the first dielectric cap layer. A select gate is formed on a sidewall of the first dielectric cap layer in a self-aligned manner. A drain diffusion region is formed in the substrate and adjacent to the select gate.

Abstract: A semiconductor memory device includes a substrate; a source diffusion region in the substrate; a pair of floating gates disposed on opposite of the source diffusion region; a first dielectric cap layer disposed directly on each of the floating gates; an erase gate disposed on the source diffusion region and partially overlapping an upper inner corner of each of the floating gates; a second dielectric cap layer disposed on the erase gate and the first dielectric cap layer; a select gate disposed on a sidewall of the first dielectric cap layer; and a drain diffusion region disposed in the substrate and adjacent to the select gate.

Abstract: A flash includes a substrate. Two gate structures are disposed on the substrate. Each of the gate structures includes a floating gate and a control gate. The control gate is disposed on the floating gate. An erase gate is disposed between the gate structures. Two word lines are respectively disposed at a side of each of the gate structures. A top surface of each of the word lines includes a first concave surface and a sharp angle. The sharp angle is closed to a sidewall of the word line which the sharp angle resided. The sidewall is away from each of the gate structures. The sharp angle connects to the first concave surface.

Abstract: A method for driving display panel includes: for one of adjacent two frames of displayed images, when scanning odd-numbered row of sub-pixels, inputting data signals to the data lines coupled to the data selector in first order by a data selector; when scanning even-numbered row of sub-pixels, inputting data signals to the data lines coupled to the data selector in second order by the data selector; first and second orders each represents an order of inputting data signals to the data lines; first order is opposite to second order; for the other of the adjacent two frames of displayed images, when scanning odd-numbered row of sub-pixels, inputting data signals to the data lines coupled to the data selector in second order by the data selector; when scanning even-numbered row of sub-pixels, inputting data signals to the data lines coupled to the data selector in first order by the data selector.

Abstract: A semiconductor memory device includes a semiconductor substrate, a select gate on the semiconductor substrate, a control gate disposed adjacent to the select gate and having a first sidewall and a second sidewall, and a charge storage layer between the control gate and the semiconductor substrate. The control gate includes a third sidewall close to the second sidewall of the select gate, a fourth sidewall opposite to the third sidewall, and a non-planar top surface between the third sidewall and the fourth sidewall. The non-planar top surface includes a first surface region that descends from the third sidewall to the fourth sidewall. The charge storage layer extends to the second sidewall of the select gate.

Abstract: A semiconductor memory device includes a substrate; a source diffusion region in the substrate; a pair of floating gates disposed on opposite of the source diffusion region; a first dielectric cap layer disposed directly on each of the floating gates; an erase gate disposed on the source diffusion region and partially overlapping an upper inner corner of each of the floating gates; a second dielectric cap layer disposed on the erase gate and the first dielectric cap layer; a select gate disposed on a sidewall of the first dielectric cap layer; and a drain diffusion region disposed in the substrate and adjacent to the select gate.

Abstract: The present disclosure provides a backlight module and a display device. The backlight module includes: a back plate including a bottom wall and a side wall coupled thereto, with the bottom wall and the side wall defining an accommodating space; a light guide plate disposed in the accommodating space and including: a light outgoing surface disposed away from the bottom wall, a bottom surface disposed toward the bottom wall, and a light incident surface coupled between the light outgoing face and the bottom face; a light source disposed in the accommodating space and configured to emit light toward the light incident surface; and a composite film located on a side of the light guide plate away from the bottom wall and including a diffuser sheet and a plurality of prism sheets combined together and sequentially arranged in a direction away from the light guide plate.

Abstract: A flash includes a substrate. Two gate structures are disposed on the substrate. Each of the gate structures includes a floating gate and a control gate. The control gate is disposed on the floating gate. An erase gate is disposed between the gate structures. Two word lines are respectively disposed at a side of each of the gate structures. A top surface of each of the word lines includes a first concave surface and a sharp angle. The sharp angle is closed to a sidewall of the word line which the sharp angle resided. The sidewall is away from each of the gate structures. The sharp angle connects to the first concave surface.

Abstract: A flash includes a substrate. Two gate structures are disposed on the substrate. Each of the gate structures includes a floating gate and a control gate. The control gate is disposed on the floating gate. An erase gate is disposed between the gate structures. Two word lines are respectively disposed at a side of each of the gate structures. A top surface of each of the word lines includes a first concave surface and a sharp angle. The sharp angle is closed to a sidewall of the word line which the sharp angle resided. The sidewall is away from each of the gate structures. The shape angle connects to the first concave surface.

Abstract: The disclosure provides an array substrate, a display panel and a displaying device, relating to the technical field of display ambient light. The array substrate has an active area and a peripheral area located on at least one side of the active area. The array substrate comprises a brightness detection module and a reference module. The brightness detection module is arranged in the peripheral area, comprising at least one first thin-film transistor. The brightness detection module is configured to receive ambient light, generate an ambient light brightness detecting current signal in response to the ambient light and output the ambient light brightness detecting current signal. The reference module is arranged in the peripheral area, comprising at least one second thin-film transistor. The reference module is configured to, in a dark state without ambient light, generate and output a reference current signal.

Abstract: A flash includes a substrate. Two gate structures are disposed on the substrate. Each of the gate structures includes a floating gate and a control gate. The control gate is disposed on the floating gate. An erase gate is disposed between the gate structures. Two word lines are respectively disposed at a side of each of the gate structures. A top surface of each of the word lines includes a first concave surface and a sharp angle. The sharp angle is closed to a sidewall of the word line which the sharp angle resided. The sidewall is away from each of the gate structures. The shape angle connects to the first concave surface.

Abstract: The present disclosure provides a backlight module and a display device. The backlight module includes: a back plate including a bottom wall and a side wall coupled thereto, with the bottom wall and the side wall defining an accommodating space; a light guide plate disposed in the accommodating space and including: a light outgoing surface disposed away from the bottom wall, a bottom surface disposed toward the bottom wall, and a light incident surface coupled between the light outgoing face and the bottom face; a light source disposed in the accommodating space and configured to emit light toward the light incident surface; and a composite film located on a side of the light guide plate away from the bottom wall and including a diffuser sheet and a plurality of prism sheets combined together and sequentially arranged in a direction away from the light guide plate.

Abstract: A method for driving display panel includes: for one of adjacent two frames of displayed images, when scanning odd-numbered row of sub-pixels, inputting data signals to the data lines coupled to the data selector in first order by a data selector; when scanning even-numbered row of sub-pixels, inputting data signals to the data lines coupled to the data selector in second order by the data selector; first and second orders each represents an order of inputting data signals to the data lines; first order is opposite to second order; for the other of the adjacent two frames of displayed images, when scanning odd-numbered row of sub-pixels, inputting data signals to the data lines coupled to the data selector in second order by the data selector; when scanning even-numbered row of sub-pixels, inputting data signals to the data lines coupled to the data selector in first order by the data selector.

Abstract: A display panel, a control method and a display apparatus are provided. The display panel includes a first display area having a notched boundary and a second display area. The first display area includes a first pixel unit group comprising X white sub-pixel or sub-pixels and Y first single color sub-pixels, and the second display area includes a second pixel unit group comprising Y second single color sub-pixels, where X is an integer of at least 1 and Y is an integer of at least 1.

Abstract: A display panel, a control method and a display apparatus are provided. The display panel includes a first display area having a notched boundary and a second display area. The first display area includes a first pixel unit group comprising X white sub-pixel or sub-pixels and Y first single color sub-pixels, and the second display area includes a second pixel unit group comprising Y second single color sub-pixels, where X is an integer of at least 1 and Y is an integer of at least 1.

Abstract: The present invention relates to a visual efficacy measuring method for objects in different light environments, which comprises: (a) setting a light environment; (b) measuring a relationship between color temperature and time; (c) a driver visually recognizing a target object; (d) resetting the light environment, and repeating the step (c); (e) processing the visual recognition information data collected by the experiments so as to establish a relationship of the visual recognition time in relation with the light environmental parameters of color temperature, color rendering index and brightness; (f) performing visual efficacy analysis according to the processing results of the visual recognition information data.

Abstract: The invention relates to an illumination standard calculation method for a tunnel entrance section in daytime based on safe visual recognition.