Patents by Inventor Xiaojue Zeng

Xiaojue Zeng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11977482
    Abstract: To avoid hash table collisions, such as in response to sequential addresses, a hash module is provided that includes a first multiplexer that, responsive to a control signal, outputs received data on one of two or more scramblers. The scramblers are configured to selectively receive the selected data output from the first multiplexer and perform a scrambler operation on the selected data to generate scrambled data. A second multiplexer outputs the scrambled data to a first hash module configured to performs a hash function on the scrambled data to generate a hash value. A second hash module, responsive to a collision occurring in the first hash module, perform a hash function on the scrambled data received from the first hash module. The use of a scrambler reduces collisions in the hash module outputs over time and multiple scramblers may be used to further reduce collisions.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: May 7, 2024
    Assignee: FLC Technology Group, Inc.
    Inventors: Rong Xu, Xiaojue Zeng, Fan Yang, Hunglin Hsu, Sehat Sutardja
  • Patent number: 11645148
    Abstract: A system and method for caching memory request verification data comprising a memory request generator configured to generate a memory request designating requested data and memory request verification data. A bus is configured to carry the memory request from the memory request generator to a cache memory that stores verification data, and upon receiving the memory request is configured to: retrieve stored verification data from the cache memory, compare the stored verification data to the memory request verification data, and responsive to a match between the stored verification data to the memory request verification data, designate a memory request validation. Also part of the system is a memory controller configured to, responsive to a memory request validation, retrieve data specified in the memory request from a main memory and provide the data to the memory request generator over the bus. A main memory configured to store the requested data.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: May 9, 2023
    Assignee: FLC Technology Group, Inc.
    Inventors: Xiaojue Zeng, Cheng Chung Wang, Fan Yang, Rong Xu, Bo Hu, Hunglin Hsu, Sehat Sutardja
  • Publication number: 20220066929
    Abstract: To avoid hash table collisions, such as in response to sequential addresses, a hash module is provided that includes a first multiplexer that, responsive to a control signal, outputs received data on one of two or more scramblers. The scramblers are configured to selectively receive the selected data output from the first multiplexer and perform a scrambler operation on the selected data to generate scrambled data. A second multiplexer outputs the scrambled data to a first hash module configured to performs a hash function on the scrambled data to generate a hash value. A second hash module, responsive to a collision occurring in the first hash module, perform a hash function on the scrambled data received from the first hash module. The use of a scrambler reduces collisions in the hash module outputs over time and multiple scramblers may be used to further reduce collisions.
    Type: Application
    Filed: September 2, 2021
    Publication date: March 3, 2022
    Inventors: Rong Xu, Xiaojue Zeng, Fan Yang, Hunglin Hsu, Sehat Sutardja
  • Publication number: 20210334158
    Abstract: A system and method for caching memory request verification data comprising a memory request generator configured to generate a memory request designating requested data and memory request verification data. A bus is configured to carry the memory request from the memory request generator to a cache memory that stores verification data, and upon receiving the memory request is configured to: retrieve stored verification data from the cache memory, compare the stored verification data to the memory request verification data, and responsive to a match between the stored verification data to the memory request verification data, designate a memory request validation. Also part of the system is a memory controller configured to, responsive to a memory request validation, retrieve data specified in the memory request from a main memory and provide the data to the memory request generator over the bus. A main memory configured to store the requested data.
    Type: Application
    Filed: April 28, 2021
    Publication date: October 28, 2021
    Inventors: Xiaojue Zeng, Cheng Chung Wang, Fan Yang, Rong Xu, Bo Hu, Hunglin Hsu, Sehat Sutardja