Patents by Inventor Xiaokang Qin

Xiaokang Qin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11385926
    Abstract: An application and system fast launch may provide a virtual memory address area (VMA) container to manage the restore of a context of a process, i.e., process context, saved in response to a checkpoint to enhance performance and to provide a resource efficient fast launch. More particularly, the fast launch may provide a way to manage, limit and/or delay the restore of a process context saved in response to a checkpoint, by generating a VMA container comprising VMA container pages, to restore physical memory pages following the checkpoint based on the most frequently used or predicted to be used. The application and system fast launch with the VMA container may avoid unnecessary input/output (I/O) bandwidth consumption, page faults and/or memory copy operations that may otherwise result from restoring the entire context of a VMA container without regard to frequency of use.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: July 12, 2022
    Assignee: Intel Corporation
    Inventors: Chao Xie, Jia Bao, Mingwei Shi, Yifan Zhang, Qiming Shi, Beiyuan Hu, Tianyou Li, Xiaokang Qin
  • Patent number: 10802979
    Abstract: Systems and techniques for dynamic code execution location in heterogeneous memory are described herein. In an system having a first class of memory and second class of memory that are both byte-addressable, an interpreter may be initialized to execute a program from the first class of memory. The initialization may include locating an Interpreter Routine Address Table (IRIT) in the second class of memory and creating counters for routines in the IRIT. A counter for a routine may be modified as it is referenced from the IRIT during execution. The routine may be moved from the first class of memory to the second class of memory in response to the counter passing a threshold. An entry in the IRIT for the routine may be updated with an address in the second class of memory corresponding to the routine.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: October 13, 2020
    Assignee: Intel Corporation
    Inventors: Shu Xu, Tianyou Li, Zidong Jiang, Weiliang Lion Lin, Jinkui Ren, Chaobo Zhu, Xiaokang Qin
  • Publication number: 20190361730
    Abstract: An application and system fast launch may provide a virtual memory address area (VMA) container to manage the restore of a context of a process, i.e., process context, saved in response to a checkpoint to enhance performance and to provide a resource efficient fast launch. More particularly, the fast launch may provide a way to manage, limit and/or delay the restore of a process context saved in response to a checkpoint, by generating a VMA container comprising VMA container pages, to restore physical memory pages following the checkpoint based on the most frequently used or predicted to be used. The application and system fast launch with the VMA container may avoid unnecessary input/output (I/O) bandwidth consumption, page faults and/or memory copy operations that may otherwise result from restoring the entire context of a VMA container without regard to frequency of use.
    Type: Application
    Filed: February 17, 2017
    Publication date: November 28, 2019
    Inventors: Chao Xie, Jia Bao, Mingwei Shi, Yifan Zhang, Qiming Shi, Beiyuan Hu, Tianyou Li, Xiaokang Qin
  • Publication number: 20190332545
    Abstract: Systems and techniques for dynamic code execution location in heterogeneous memory are described herein. In an system having a first class of memory and second class of memory that are both byte-addressable, an interpreter may be initialized to execute a program from the first class of memory. The initialization may include locating an Interpreter Routine Address Table (IRIT) in the second class of memory and creating counters for routines in the IRIT. A counter for a routine may be modified as it is referenced from the IRIT during execution. The routine may be moved from the first class of memory to the second class of memory in response to the counter passing a threshold. An entry in the IRIT for the routine may be updated with an address in the second class of memory corresponding to the routine.
    Type: Application
    Filed: January 27, 2017
    Publication date: October 31, 2019
    Inventors: Shu Xu, Tianyou Li, Zidong Jiang, Weiliang Lion Lin, Jinkui Ren, Chaobo Zhu, Xiaokang Qin