Abstract: Embodiments of this specification provide a communication method and apparatus based on a relay cluster. The relay cluster includes a load balancing server and at least two relay servers. The communication method includes: receiving a relay request packet sent by a client, where the relay request packet includes a transaction identifier, and the transaction identifier includes a mode field and a routing information field; acquiring routing information of a first relay server of the at least two relay servers based on a value of the mode field and a value of the routing information field in the relay request packet; and sending a relay allocation packet carrying the routing information of the first relay server to the client, so that the client establishes a relay channel based on the routing information of the first relay server.

Abstract: An application and system fast launch may provide a virtual memory address area (VMA) container to manage the restore of a context of a process, i.e., process context, saved in response to a checkpoint to enhance performance and to provide a resource efficient fast launch. More particularly, the fast launch may provide a way to manage, limit and/or delay the restore of a process context saved in response to a checkpoint, by generating a VMA container comprising VMA container pages, to restore physical memory pages following the checkpoint based on the most frequently used or predicted to be used. The application and system fast launch with the VMA container may avoid unnecessary input/output (I/O) bandwidth consumption, page faults and/or memory copy operations that may otherwise result from restoring the entire context of a VMA container without regard to frequency of use.

Abstract: Systems and techniques for dynamic code execution location in heterogeneous memory are described herein. In an system having a first class of memory and second class of memory that are both byte-addressable, an interpreter may be initialized to execute a program from the first class of memory. The initialization may include locating an Interpreter Routine Address Table (IRIT) in the second class of memory and creating counters for routines in the IRIT. A counter for a routine may be modified as it is referenced from the IRIT during execution. The routine may be moved from the first class of memory to the second class of memory in response to the counter passing a threshold. An entry in the IRIT for the routine may be updated with an address in the second class of memory corresponding to the routine.

Abstract: An application and system fast launch may provide a virtual memory address area (VMA) container to manage the restore of a context of a process, i.e., process context, saved in response to a checkpoint to enhance performance and to provide a resource efficient fast launch. More particularly, the fast launch may provide a way to manage, limit and/or delay the restore of a process context saved in response to a checkpoint, by generating a VMA container comprising VMA container pages, to restore physical memory pages following the checkpoint based on the most frequently used or predicted to be used. The application and system fast launch with the VMA container may avoid unnecessary input/output (I/O) bandwidth consumption, page faults and/or memory copy operations that may otherwise result from restoring the entire context of a VMA container without regard to frequency of use.

Abstract: Systems and techniques for dynamic code execution location in heterogeneous memory are described herein. In an system having a first class of memory and second class of memory that are both byte-addressable, an interpreter may be initialized to execute a program from the first class of memory. The initialization may include locating an Interpreter Routine Address Table (IRIT) in the second class of memory and creating counters for routines in the IRIT. A counter for a routine may be modified as it is referenced from the IRIT during execution. The routine may be moved from the first class of memory to the second class of memory in response to the counter passing a threshold. An entry in the IRIT for the routine may be updated with an address in the second class of memory corresponding to the routine.