Patents by Inventor Xiaokang Wang

Xiaokang Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11933282
    Abstract: An inductive plasma acceleration apparatus, comprising a pulse laser assembly, a pulsed discharge assembly, an exciting coil assembly, a solid-state working medium, and a control assembly; the exciting coil assembly is electrically connected to the pulsed discharge assembly such that a strong pulse current is produced in the exciting coil assembly during the discharge process of the pulse discharge assembly, and an inductive pulse electromagnetic field is excited around the exciting coil assembly; the solid-state working medium is positioned on the optical path of a pulse laser emitted by the pulse laser assembly such that the solid-state working medium produces a pulse gas under the ablation action of the pulse laser, and the inductive pulse electromagnetic field is positioned on the circulation gas path of the pulse gas such that the pulse gas can enter the inductive pulse electromagnetic field.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: March 19, 2024
    Assignee: NATIONAL UNIVERSITY OF DEFENSE TECHNOLOGY
    Inventors: Xiaokang Li, Mousen Cheng, Jianjun Wu, Bixuan Che, Moge Wang, Dawei Guo, Xiong Yang
  • Patent number: 11231610
    Abstract: The present disclosure is related to a display panel. The display panel may include a first light shielding layer (101) in a display region and a second light shielding layer (212) opposite the first light shielding layer (101) in the display region. The first light shielding layer (101) may include a plurality of first openings (112), and the second light shielding layer (212) may include a plurality of second openings (222). The display region may include a middle display region (20A) and a periphery display region (20B). An area of each of the plurality of the first openings (112) in the periphery display region (20B) may be smaller than an area of each of the plurality of the first openings (112) in the middle display region (20A).
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: January 25, 2022
    Assignees: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xiaokang Wang, Yanqing Chen, Jianyun Xie, Wei Li, Cheng Li, Le Sun, Wei Zhang, Xin Zhao, Zhijun Niu, Yezhou Fang, Pan Guo, Yanfeng Li, Weida Qin, Ning Wang
  • Publication number: 20210325719
    Abstract: The present disclosure is related to a display panel. The display panel may include a first light shielding layer (101) in a display region and a second light shielding layer (212) opposite the first light shielding layer (101) in the display region. The first light shielding layer (101) may include a plurality of first openings (112), and the second light shielding layer (212) may include a plurality of second openings (222). The display region may include a middle display region (20A) and a periphery display region (20B). An area of each of the plurality of the first openings (112) in the periphery display region (20B) may be smaller than an area of each of the plurality of the first openings (112) in the middle display region (20A).
    Type: Application
    Filed: July 19, 2018
    Publication date: October 21, 2021
    Applicants: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE Technology Group Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Xiaokang Wang, Yanqing Chen, Jianyun Xie, Wei Li, Cheng Li, Le Sun, Wei Zhang, Xin Zhao, Zhijun Niu, Yezhou Fang, Pan Guo, Yanfeng Li, Weida Qin, Ning Wang
  • Patent number: 11145682
    Abstract: An array substrate which includes a display region and a peripheral region surrounding the display region, the peripheral region includes a data line lead region and a driving circuit region, and the data line lead region is between the driving circuit region and the display region; the driving circuit region includes a driving circuit, the data line lead region includes a the plurality of data line leads, and the plurality of data line leads extend from the display region and are electrically connected with the driving circuit; and the data line lead region includes peripheral data line leads, a region of the peripheral region close to the peripheral data line leads includes at least one retaining wall configured to prevent plasma from affecting the peripheral data line leads. A method for fabricating an array substrate, a display panel, and a display device are also disclosed.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: October 12, 2021
    Assignees: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yanan Yu, Jingyi Xu, Yanwei Ren, Xin Zhao, Xiaokang Wang, Yuelin Wang, Huijie Zhang
  • Publication number: 20210232014
    Abstract: An electrochromic device, including a first transparent conductor layer, an electrochromic layer, a toughened interface layer positioned between and operationally connected in electric communication with the first transparent conductor layer and the electrochromic layer, an electrolyte operationally connected to the electrochromic layer, an ion storage layer operationally connected to the solid electrolyte layer, and a second transparent conductor layer operationally connected to the ion storage layer. The electrochromic device remains substantially free of interfacial delamination between the first transparent conductive and the electrochromic layer for at least 10,000 duty cycles.
    Type: Application
    Filed: December 18, 2020
    Publication date: July 29, 2021
    Inventors: Jianguo Mei, Kejie Zhao, Ke Chen, Xiaokang Wang
  • Patent number: 10700105
    Abstract: An array substrate, a method for manufacturing an array substrate, a display panel and a display device are provided. The array substrate includes: a base substrate including a display area and a non-display area; a dummy data line in the non-display area of the base substrate; and an effective data line in the non-display area of the base substrate. The dummy data line is closer to an edge of the base substrate than the effective data line, and a width of the dummy data line is greater than a width of the effective data line.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: June 30, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Yanfeng Li, Yanan Yu, Jingyi Xu, Xin Zhao, Xiaokang Wang, Yanwei Ren, Wei Li
  • Publication number: 20200168639
    Abstract: An array substrate which includes a display region and a peripheral region surrounding the display region, the peripheral region includes a data line lead region and a driving circuit region, and the data line lead region is between the driving circuit region and the display region; the driving circuit region includes a driving circuit, the data line lead region includes a the plurality of data line leads, and the plurality of data line leads extend from the display region and are electrically connected with the driving circuit; and the data line lead region includes peripheral data line leads, a region of the peripheral region close to the peripheral data line leads includes at least one retaining wall configured to prevent plasma from affecting the peripheral data line leads. A method for fabricating an array substrate, a display panel, and a display device are also disclosed.
    Type: Application
    Filed: March 13, 2019
    Publication date: May 28, 2020
    Inventors: Yanan YU, Jingyi XU, Yanwei REN, Xin ZHAO, Xiaokang WANG, Yuelin WANG, Huijie ZHANG
  • Publication number: 20190164997
    Abstract: An array substrate, a method for manufacturing an array substrate, a display panel and a display device are provided. The array substrate includes: a base substrate including a display area and a non-display area; a dummy data line in the non-display area of the base substrate; and an effective data line in the non-display area of the base substrate. The dummy data line is closer to an edge of the base substrate than the effective data line, and a width of the dummy data line is greater than a width of the effective data line.
    Type: Application
    Filed: September 14, 2018
    Publication date: May 30, 2019
    Inventors: Yanfeng Li, Yanan Yu, Jingyi Xu, Xin Zhao, Xiaokang Wang, Yanwei Ren, Wei Li