Abstract: A path verification method in a logic circuit includes determining a plurality of first paths that are to be tested in a design for test (DFT) mode, determining a plurality of second paths that are to be tested in a function mode, determining a third path in the plurality of first paths and the plurality of second paths that does not need to achieve optimal performance in the function mode, and setting a time sequence constraint for the third path in the function mode to cause the third path to achieve target performance within a number AA clock cycles. AA is less than or equal to a ratio of a clock frequency in the function mode to a clock frequency in the DFT mode. AA is a positive integer.

Abstract: An integrated circuit physical design wiring and optimization method includes, in a first physical design wiring process, performing physical design wiring with a weight of each of one or more signal lines set to a first weight and a weight of a clock line set to a second weight, extracting a violation signal line with a time sequence violation during the first physical design wiring process, and in a second physical design wiring process, reperforming physical design wiring on the violation signal line, a remaining signal line other than the violation signal line, and the clock line with the weight of the violation signal line set to a third weight greater than the first weight. The first weight is less than or equal to the second weight.

Abstract: A chip design method includes determining a to-be-designed second device in a second module, arranging a second device in the first module, connecting the interface of the first device in the first module and the interface of the second device in the first module, performing physical design by analyzing physical wiring and time sequence convergence between the first device in the first module and the second device, copying the second device in the first module after the physical design as a designed second device in the second module, and disconnecting the interface of the first device in the first module from the interface of the second device in the first module and connecting the interface of the first device in the first module to an interface of the designed second device in the second module.

Abstract: A clock design method for two or more physical partition structures based on a same system clock. The method includes determining a distance of each circuit logic from the system clock; based on the distance between each circuit logic and the system clock, obtaining a plurality of clock nodes from the system clock to cause a delay of each clock node compared to the system clock to change with the distance from each circuit logic and the system clock, the greater the distance, the greater the delay; connecting each circuit logic to a corresponding clock node based on size of each circuit logic and the distance; and converging timing of each circuit logic by adjusting the delay of each clock node compared to the system clock.