Patents by Inventor Xiaolei Cai

Xiaolei Cai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240174648
    Abstract: Provided is a small molecule compound, which is characterized in having the structure represented by the following molecular formula: (I), wherein X1 and X2 are selected from carbon or nitrogen; G1 is a carbocyclic ring or heterocyclic ring having aromaticity; any one or more hydrogen atoms on the ring of G1 are substituted by R1; and R1 is selected from nitrogen-containing groups. The small molecule compound of the present invention can be used as a highly effective and specific JAK kinase inhibitor, specifically a Tyk2 inhibitor; and/or a JAK1 inhibitor, and/or a JAK1/Tyk2 or Tyk2/JAK1, Tyk2/Jak2 dual inhibitor.
    Type: Application
    Filed: October 10, 2020
    Publication date: May 30, 2024
    Inventors: Li Xing, Guanqun Li, Xiaolei Wang, Yuting Cai, Xiang Jiang, Xiang Pan, Wenhao Zhu, Yang Wang, Zengquan Wang
  • Patent number: 11334698
    Abstract: Disclosed is cell-aware defect characterization by considering inter-cell timing. Also disclosed is a method and apparatus that determines whether a defect can be detected in a standard library cell used to design an integrated circuit. A defect detection table is generated that indicates whether particular defects can be detected with particular combinations of input logic states and under varying load conditions. Results are merged to provide a single metric for each combination of input and output logic states that indicates one of three possible results for each defect: (1) whether the defect can be detected under all load conditions, (2) whether the defect can be detected only under some load conditions; or (3) whether the defect cannot be detected for the particular combination of input logic states regardless of the load conditions.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: May 17, 2022
    Assignee: Synopsys, Inc.
    Inventors: Ruifeng Guo, Emil Gizdarski, Xiaolei Cai
  • Publication number: 20210342511
    Abstract: Disclosed is cell-aware defect characterization by considering inter-cell timing. Also disclosed is a method and apparatus that determines whether a defect can be detected in a standard library cell used to design an integrated circuit. A defect detection table is generated that indicates whether particular defects can be detected with particular combinations of input logic states and under varying load conditions. Results are merged to provide a single metric for each combination of input and output logic states that indicates one of three possible results for each defect: (1) whether the defect can be detected under all load conditions, (2) whether the defect can be detected only under some load conditions; or (3) whether the defect cannot be detected for the particular combination of input logic states regardless of the load conditions.
    Type: Application
    Filed: April 29, 2021
    Publication date: November 4, 2021
    Inventors: Ruifeng Guo, Emil Gizdarski, Xiaolei Cai
  • Patent number: 10528692
    Abstract: A cell-aware defect characterization method includes partitioning a multibit cell netlist file into multiple single-bit partition netlist files, and then generating a cell-aware test model for each partition netlist file. Partitioning is performed such that each partition netlist file includes a corresponding flip-flop along with input, output and control pins that are operably coupled to the input, output and control terminals of the corresponding flip-flop, and all active, passive and parasitic circuit elements that are coupled in the signal paths extending between the corresponding flip-flop and the input/output/control pins. Shared resources (e.g., clock or scan select pins and associated signal lines) that are utilized by two or more flip-flops are included in each associated partition. The partitioning process is performed using either a structural back-tracing approach or a logic simulation approach.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: January 7, 2020
    Assignee: Synopsis, Inc.
    Inventors: Ruifeng Guo, Brian M. Archer, Kevin Chau, Xiaolei Cai
  • Patent number: 10515167
    Abstract: A computer-implemented method for characterizing a circuit is presented. The method includes receiving, by the computer, data representative of the circuit and at least one defect of the circuit. The method further includes simulating, using the computer, the circuit to obtain a first timing characteristic, and simulating, using the computer, the circuit with the at least one defect to obtain a second timing characteristic. The method further includes identifying, using the computer, an association between at least one test vector and the at least one defect in accordance with the first timing characteristic, the second timing characteristic, and a multitude of strobes applied during a first time interval associated with the at least one test vector, when the computer is invoked to characterize the circuit.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: December 24, 2019
    Assignee: SYNOPSYS, INC.
    Inventors: Ruifeng Guo, Brian Matthew Archer, William Albert Lloyd, Christopher Kevin Allsup, Xiaolei Cai, Kevin Chau
  • Publication number: 20180039721
    Abstract: A computer-implemented method for characterizing a circuit is presented. The method includes receiving, by the computer, data representative of the circuit and at least one defect of the circuit. The method further includes simulating, using the computer, the circuit to obtain a first timing characteristic, and simulating, using the computer, the circuit with the at least one defect to obtain a second timing characteristic. The method further includes identifying, using the computer, an association between at least one test vector and the at least one defect in accordance with the first timing characteristic, the second timing characteristic, and a multitude of strobes applied during a first time interval associated with the at least one test vector, when the computer is invoked to characterize the circuit.
    Type: Application
    Filed: August 5, 2016
    Publication date: February 8, 2018
    Inventors: Ruifeng Guo, Brian Matthew Archer, William Albert Lloyd, Christopher Kevin Allsup, Xiaolei Cai, Kevin Chau