Patents by Inventor Xiaolei Man

Xiaolei Man has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250060909
    Abstract: A system includes a memory and a processing device, operatively coupled to the memory, to perform operations including initiating a write operation in a first mode to write a first portion of data to a cache, determining whether a logical saturation of the first portion of the data satisfies a first threshold condition based on the first maximum size, and in response to determining that the logical saturation of the first portion of the data satisfies the first threshold condition, continuing the write operation in the second mode to write a second portion of the data to the cache. The cache has a first maximum size corresponding to the first mode and a second maximum size greater than the first maximum size corresponding to a second mode.
    Type: Application
    Filed: October 31, 2024
    Publication date: February 20, 2025
    Inventors: Roy Leonard, Xiaolei Man, Bryan Li, Peijing Ye
  • Patent number: 12182452
    Abstract: A system includes a memory and a processing device, operatively coupled to the memory, to perform operations including initiating a write operation in a first mode to write a first portion of data to a single-level cell (SLC) cache, determining whether a logical saturation of the first portion of the data satisfies a first threshold condition based on the first maximum size, and in response to determining that the logical saturation of the first portion of the data satisfies the first threshold condition, continuing the write operation in the second mode to write a second portion of the data to the SLC cache. The SLC cache includes a dynamic SLC cache having a first maximum size corresponding to the first mode and a second maximum size greater than the first maximum size corresponding to a second mode.
    Type: Grant
    Filed: November 7, 2023
    Date of Patent: December 31, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Roy Leonard, Xiaolei Man, Bryan Li, Peijing Ye
  • Publication number: 20240078047
    Abstract: A system includes a memory and a processing device, operatively coupled to the memory, to perform operations including initiating a write operation in a first mode to write a first portion of data to a single-level cell (SLC) cache, determining whether a logical saturation of the first portion of the data satisfies a first threshold condition based on the first maximum size, and in response to determining that the logical saturation of the first portion of the data satisfies the first threshold condition, continuing the write operation in the second mode to write a second portion of the data to the SLC cache. The SLC cache includes a dynamic SLC cache having a first maximum size corresponding to the first mode and a second maximum size greater than the first maximum size corresponding to a second mode.
    Type: Application
    Filed: November 7, 2023
    Publication date: March 7, 2024
    Inventors: Roy Leonard, Xiaolei Man, Bryan Li, Peijing Ye
  • Patent number: 11861234
    Abstract: A method includes receiving data to write to a memory sub-system including a single-level cell (SLC) cache and a multiple level cell (XLC) storage. The SLC cache includes a static SLC cache having a fixed size, and dynamic SLC cache having a default maximum size corresponding to a first mode of operation and an enhanced maximum size greater than the default maximum size corresponding to a second mode of operation. The method further includes, in response to determining to initiate a write operation in a first mode, initiating the write operation in the first mode to write a first portion of the data to the SLC cache, and in response to determining that a logical saturation of the first portion of the data satisfies the first threshold condition, continuing the write operation in the second mode to write a second portion of the data to the SLC cache.
    Type: Grant
    Filed: March 18, 2022
    Date of Patent: January 2, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Roy Leonard, Xiaolei Man, Bryan Li, Peijing Ye
  • Publication number: 20230297279
    Abstract: A method includes receiving data to write to a memory sub-system including a single-level cell (SLC) cache and a multiple level cell (XLC) storage. The SLC cache includes a static SLC cache having a fixed size, and dynamic SLC cache having a default maximum size corresponding to a first mode of operation and an enhanced maximum size greater than the default maximum size corresponding to a second mode of operation. The method further includes, in response to determining to initiate a write operation in a first mode, initiating the write operation in the first mode to write a first portion of the data to the SLC cache, and in response to determining that a logical saturation of the first portion of the data satisfies the first threshold condition, continuing the write operation in the second mode to write a second portion of the data to the SLC cache.
    Type: Application
    Filed: March 18, 2022
    Publication date: September 21, 2023
    Inventors: Roy Leonard, Xiaolei Man, Bryan Li, Peijing Ye