Abstract: An apparatus is disclosed for adaptive multi-mode charging. In an example aspect, the apparatus includes at least one charger having a first node and a second node. The at least one charger is configured to accept an input voltage at the first node. The at least one charger is also configured to selectively operate in a first mode to generate a first output voltage at the second node that is greater than or less than the input voltage or operate in a second mode to generate a second output voltage at the second node that is substantially equal to the input voltage.

Abstract: An apparatus is disclosed for adaptive multi-mode charging. In an example aspect, the apparatus includes at least one charger having a first node and a second node. The at least one charger is configured to accept an input voltage at the first node. The at least one charger is also configured to selectively operate in a first mode to generate a first output voltage at the second node that is greater than or less than the input voltage or operate in a second mode to generate a second output voltage at the second node that is substantially equal to the input voltage.

Abstract: An apparatus is disclosed for adaptive multi-mode charging. In an example aspect, the apparatus includes at least one charger having a first node and a second node. The at least one charger is configured to accept an input voltage at the first node. The at least one charger is also configured to selectively operate in a first mode to generate a first output voltage at the second node that is greater than or less than the input voltage or operate in a second mode to generate a second output voltage at the second node that is substantially equal to the input voltage.

Abstract: An apparatus is disclosed for adaptive multi-mode charging. In an example aspect, the apparatus includes at least one charger having a first node and a second node. The at least one charger is configured to accept an input voltage at the first node. The at least one charger is also configured to selectively operate in a first mode to generate a first output voltage at the second node that is greater than or less than the input voltage or operate in a second mode to generate a second output voltage at the second node that is substantially equal to the input voltage.

Abstract: Techniques and apparatus for current-based transitioning between a buck converter mode and a charge pump mode in an adaptive combination power supply circuit. One example power supply circuit generally includes a switching regulator and control logic coupled to the switching regulator. The control logic is generally configured to compare an indication of a current associated with the switching regulator to a threshold and to control a transition of the switching regulator between a buck converter mode and a charge pump mode based on the comparison.

Abstract: A method of operating a buck converter is disclosed. The buck converter includes a first capacitor, a second capacitor, and an inductor between a node and an output of the buck converter. The method includes, during a first portion of a cycle, coupling the first capacitor and the second capacitor in series between an input of the buck converter and a ground, wherein the first capacitor is coupled between the input of the buck converter and the node, and the second capacitor is coupled between the node and the ground. The method also includes, during a second portion of the cycle, coupling the second capacitor and the first capacitor in series between the input of the buck converter and the ground, wherein the second capacitor is coupled between the input of the buck converter and the node, and the first capacitor is coupled between the node and the ground.

Abstract: Techniques and apparatus for current-based transitioning between a buck converter mode and a charge pump mode in an adaptive combination power supply circuit. One example power supply circuit generally includes a switching regulator and control logic coupled to the switching regulator. The control logic is generally configured to compare an indication of a current associated with the switching regulator to a threshold and to control a transition of the switching regulator between a buck converter mode and a charge pump mode based on the comparison.

Abstract: A method of operating a buck converter is disclosed. The buck converter includes a first capacitor, a second capacitor, and an inductor between a node and an output of the buck converter. The method includes, during a first portion of a cycle, coupling the first capacitor and the second capacitor in series between an input of the buck converter and a ground, wherein the first capacitor is coupled between the input of the buck converter and the node, and the second capacitor is coupled between the node and the ground. The method also includes, during a second portion of the cycle, coupling the second capacitor and the first capacitor in series between the input of the buck converter and the ground, wherein the second capacitor is coupled between the input of the buck converter and the node, and the first capacitor is coupled between the node and the ground.

Abstract: An apparatus is disclosed for adaptive multi-mode charging. In an example aspect, the apparatus includes at least one charger having a first node and a second node. The at least one charger is configured to accept an input voltage at the first node. The at least one charger is also configured to selectively operate in a first mode to generate a first output voltage at the second node that is greater than or less than the input voltage or operate in a second mode to generate a second output voltage at the second node that is substantially equal to the input voltage.

Abstract: Systems, methods, and apparatus for a circuit with power factor correction (PFC) are disclosed. In one or more embodiments, the disclosed method comprises providing, by a single-stage power converter, a delay in phase between a peak current command and a rectified input voltage such that a phase of a transformer current intentionally lags behind a phase of the rectified input voltage to maintain a power factor (PF) level and a total harmonic distortion (THD) level for the single-stage power converter. In one or more analog embodiments, a resistor and a capacitor are implemented into a conventional single-stage power converter to provide the delay in phase between the peak current command and the rectified input voltage. In one or more digital embodiments, a controller within a conventional single-stage power converter exclusively provides the delay in phase between the peak current command and the rectified input voltage.

Abstract: A flyback converter controller is provided with a single terminal through which the flyback converter controller senses for over-voltage faults for an input voltage and also senses for open circuit faults for an auxiliary winding. A first voltage divider provides a divided version of the input voltage to the single terminal. The controller compares a voltage for the single terminal to at least one over-voltage threshold to detect the over-voltage fault for the input voltage.

Abstract: An electronic device is provided that includes an integrated circuit (IC) configured to regulate an output voltage for powering a light emitting diode (LED). A first transistor is configured to be switched on or off by the IC to inductively couple or decouple a main power supply bus voltage from a primary winding of a transformer to a secondary winding of the transformer connectable to the LED. A second transistor is coupled between the IC and the main power supply bus voltage, and configured to be switched on or off by the IC to selectively provide an IC power supply input voltage to the IC.

Abstract: An electronic that includes an integrated circuit (IC) configured to regulate an output voltage for powering a light emitting diode (LED). A first transistor is configured to be switched on or off by the IC to inductively couple or decouple a main power supply bus voltage from a primary winding of a transformer to a secondary winding of the transformer connectable to the LED. A second transistor is coupled between the IC and the main power supply bus voltage, and configured to be switched on or off by the IC to selectively provide an IC power supply input voltage to the IC.

Abstract: Systems, methods, and apparatus for a circuit with power factor correction (PFC) are disclosed. In one or more embodiments, the disclosed method comprises providing, by a single-stage power converter, a delay in phase between a peak current command and a rectified input voltage such that a phase of a transformer current intentionally lags behind a phase of the rectified input voltage to maintain a power factor (PF) level and a total harmonic distortion (THD) level for the single-stage power converter. In one or more analog embodiments, a resistor and a capacitor are implemented into a conventional single-stage power converter to provide the delay in phase between the peak current command and the rectified input voltage. In one or more digital embodiments, a controller within a conventional single-stage power converter exclusively provides the delay in phase between the peak current command and the rectified input voltage.

Abstract: Systems, methods, and apparatus for a circuit with adaptive switching frequency control are disclosed. The method comprises operating a controller of the dimmable single-stage power converter in pulse width modulation (PWM) mode at a first switching frequency level from a maximum dimming duty-ratio level until a first dimming duty-ratio level. The method further comprises operating the controller in PWM mode, while reducing switching frequency from the first switching frequency level to a second switching frequency level, from the first dimming duty-ratio level until a second dimming duty-ratio level. Also, the method comprises operating the controller in PWM mode at the second switching frequency level from the second dimming duty-ratio level until a current command (Vipk) falls below a predetermined low limit value. Further, the method comprises operating the controller in skip mode, while reducing the switching frequency from the second switching frequency level, until a minimum dimming duty-ratio level.

Abstract: A switching power converter controller is provided that includes a VCC charging switch transistor coupled between a drain of a power switch transistor and a storage capacitor.

Abstract: Systems, methods, and apparatus for a circuit with power factor correction (PFC) are disclosed. In one or more embodiments, the disclosed method comprises providing, by a single-stage power converter, a delay in phase between a peak current command and a rectified input voltage such that a phase of a transformer current intentionally lags behind a phase of the rectified input voltage to maintain a power factor (PF) level and a total harmonic distortion (THD) level for the single-stage power converter. In one or more analog embodiments, a resistor and a capacitor are implemented into a conventional single-stage power converter to provide the delay in phase between the peak current command and the rectified input voltage. In one or more digital embodiments, a controller within a conventional single-stage power converter exclusively provides the delay in phase between the peak current command and the rectified input voltage.

Abstract: An electronic that includes an integrated circuit (IC) configured to regulate an output voltage for powering a light emitting diode (LED). A first transistor is configured to be switched on or off by the IC to inductively couple or decouple a main power supply bus voltage from a primary winding of a transformer to a secondary winding of the transformer connectable to the LED. A second transistor is coupled between the IC and the main power supply bus voltage, and configured to be switched on or off by the IC to selectively provide an IC power supply input voltage to the IC.

Abstract: A switching power converter is provided that extrapolates from a reference voltage during dead periods of a rectified input voltage as determined from a comparison of an Isense voltage to a current threshold.

Abstract: A switching power converter is provided that extrapolates from a reference voltage during dead periods of a rectified input voltage as determined from a comparison of an Isense voltage to a current threshold.