Abstract: A method including creating a first bus guide and a second bus guide of a plurality of bus guides for an integrated circuit is disclosed. The method includes routing the first bus guide and the second bus guide through a plurality of layout blocks of the integrated circuit. The method includes annotating the first bus guide or the second bus guide to identify a plurality of areas for placing a plurality of repeaters within the first bus guide or the second bus guide. The method includes, based on the annotated first bus guide and the second bus guide, generating, by at least one processor, a plurality of guidance directories corresponding to a plurality of routes through the plurality of layout blocks for placing the plurality of repeaters at the plurality of layout blocks on the identified plurality of areas on the first bus guide or the second bus guide.

Abstract: A method includes generating a first bitmap for a cell. The first bitmap is indicative of mapping constraints of the cell. The method also includes generating a second bitmap for a PSC filler cell. The second bitmap is indicative of the mapping constraints of the PSC filler cell. The method also includes a bitwise logical operation between a portion of the first bitmap and a respective portion of the second bitmap and determining a compatibility between the cell and the PSC filler cell based on at least a result of the bitwise logical operation.

Abstract: A method including creating a first bus guide and a second bus guide of a plurality of bus guides for an integrated circuit is disclosed. The method includes routing the first bus guide and the second bus guide through a plurality of layout blocks of the integrated circuit. The method includes annotating the first bus guide or the second bus guide to identify a plurality of areas for placing a plurality of repeaters within the first bus guide or the second bus guide. The method includes, based on the annotated first bus guide and the second bus guide, generating, by at least one processor, a plurality of guidance directories corresponding to a plurality of routes through the plurality of layout blocks for placing the plurality of repeaters at the plurality of layout blocks on the identified plurality of areas on the first bus guide or the second bus guide.

Abstract: The present disclosure provides a microcontroller unit and its fabrication method. The microcontroller unit includes a logic control substrate, and also includes at least one memory die and at least one non-memory die, which are disposed on the logic control substrate. The logic control substrate includes a semiconductor device layer and an interconnection dielectric layer. A central processing unit and at least one logic controller are formed in the semiconductor device layer. All memory dies are disposed on the interconnection dielectric layer side by side or stacked one over another, and the at least one memory die is electrically connected to the central processing unit through a corresponding electrical interconnection structure in the interconnection dielectric layer.

Abstract: A method includes generating a first bitmap for a cell. The first bitmap is indicative of mapping constraints of the cell. The method also includes generating a second bitmap for a PSC filler cell. The second bitmap is indicative of the mapping constraints of the PSC filler cell. The method also includes a bitwise logical operation between a portion of the first bitmap and a respective portion of the second bitmap and determining a compatibility between the cell and the PSC filler cell based on at least a result of the bitwise logical operation.

Abstract: The present disclosure provides a microcontroller unit and its fabrication method. The microcontroller unit includes a logic control substrate, and also includes at least one memory die and at least one non-memory die, which are disposed on the logic control substrate. The logic control substrate includes a semiconductor device layer and an interconnection dielectric layer. A central processing unit and at least one logic controller are formed in the semiconductor device layer. All memory dies are disposed on the interconnection dielectric layer side by side or stacked one over another, and the at least one memory die is electrically connected to the central processing unit through a corresponding electrical interconnection structure in the interconnection dielectric layer.

Abstract: In one example a pulse measurement system, comprises at least one sensor positioned to collect pulse information at three separate locations along a body segment, a controller communicatively coupled to the at least one sensor to receive the pulse information from the at least one sensor, and a display coupled to the controller to present at least one characteristic of the pulse information detected at the three separate locations. Other examples may be described.

Abstract: A circuit for use with a photodetector includes multiple switches, a comparator, and a capacitor. The photodetector receives a first voltage and a second voltage at first and second nodes, respectively. The first voltage is higher than the second voltage. The capacitor is connected to the first node. During a power up sequence, the capacitor is charged to the first voltage. The comparator detects when the voltage at the first node reaches a predetermined threshold and in response causes a switch to close so that the second node can receive the second voltage. In a power down sequence, the first and second nodes are allowed to discharge, with the capacitor slowing the discharge of the first node. The comparator detects when the voltage at the first node reaches a predetermined threshold and in response causes another switch to short the second node to ground.

Abstract: A method and apparatus for a low power, multi-level GTL interface signaling FSB buffer with fast restoration of static bias are described. The buffer includes a dynamic bias circuit to clamp a pad voltage level to a termination voltage level Vtt in response to a rising signal transition at the pad. By pulling-down a node voltage from a static voltage level to a dynamic voltage level, the pad voltage level is prevented from overshooting Vtt. A static bias circuit is used to maintain the node voltage at the static voltage level. A dynamic resistance unit aids the static bias circuit in restoring the node voltage level to the static voltage level once the rising signal transition is complete. Consequently, a duration of the clamping of the pad voltage level is minimized and power for clamping the pad voltage level to Vtt is reduced.

Abstract: A method and apparatus for a multi-level GTL interface signaling buffer utilizing midrail buffer pad clamping are described. The system includes a buffer having a P-kicker pull-up device which pulls up a pad voltage level to an intended overshoot level. A pull-down device pulls down the pad voltage level to a termination voltage level VTT. Consequently, the P-kicker pull-up device and the pull-down device counteract one another to generate a low-voltage midrail overshoot level that is less than or equal to a maximum gate voltage level. The midrail overshoot level that is less than or equal to the maximum gate voltage level in order to prevent gate oxide breakdown to CPU LVGTL input buffer circuits caused by overshoot levels in excess of a maximum gauge voltage level.

Abstract: A circuit for use with a photodetector includes multiple switches, a comparator, and a capacitor. The photodetector receives a first voltage and a second voltage at first and second nodes, respectively. The first voltage is higher than the second voltage. The capacitor is connected to the first node. During a power up sequence, the capacitor is charged to the first voltage. The comparator detects when the voltage at the first node reaches a predetermined threshold and in response causes a switch to close so that the second node can receive the second voltage. In a power down sequence, the first and second nodes are allowed to discharge, with the capacitor slowing the discharge of the first node. The comparator detects when the voltage at the first node reaches a predetermined threshold and in response causes another switch to short the second node to ground.

Abstract: A method and apparatus for a multi-level GTL interface signaling buffer utilizing midrail buffer pad clamping are described. The system includes a buffer having a P-kicker pull-up device which pulls up a pad voltage level to an intended overshoot level. A pull-down device pulls down the pad voltage level to a termination voltage level VTT. Consequently, the P-kicker pull-up device and the pull-down device counteract one another to generate a low-voltage midrail overshoot level that is less than or equal to a maximum gate voltage level. The midrail overshoot level that is less than or equal to the maximum gate voltage level in order to prevent gate oxide breakdown to CPU LVGTL input buffer circuits caused by overshoot levels in excess of a maximum gauge voltage level.

Abstract: A method and apparatus for a low power, multi-level GTL interface signaling FSB buffer with fast restoration of static bias are described. The buffer includes a dynamic bias circuit to clamp a pad voltage level to a termination voltage level Vtt in response to a rising signal transition at the pad. By pulling-down a node voltage from a static voltage level to a dynamic voltage level, the pad voltage level is prevented from overshooting Vtt. A static bias circuit is used to maintain the node voltage at the static voltage level. A dynamic resistance unit aids the static bias circuit in restoring the node voltage level to the static voltage level once the rising signal transition is complete. Consequently, a duration of the clamping of the pad voltage level is minimized and power for clamping the pad voltage level to Vtt is reduced.