Abstract: A solvent-free and ligand-free ball milling method for preparation of cesium lead tribromide (CsPbBr3) quantum dot is provided. First, mixing a Cs source, a Pb source, and a Br source as per a molar ratio of Cs source:Pb source:Br source is 1:1˜6:1˜9, and then adding polymethyl methacrylate (PMMA) to obtain a mixture. The mixture is milled for 1-2 hours at a rotation speed in a range of 360˜630 revolutions per minute (r/min) in a ball milling device, obtaining CsPbBr3 quantum dot. The method has advantages such as simple process, easy industrial production, no solvent, no organic ligand, low cost, and environmental protection. A quantum yield of product obtained by the method is up to 78%, and the product has a strong environmental stability. A preparation temperature of the product is low, and the reaction can be completed at a room temperature without a high temperature treatment.

Abstract: Methods and devices to improve nonlinearity performance of low noise amplifiers (LNAs) are disclosed. The described methods and devices reduce the capacitive loading of the LNA amplifying devices on the bypass path of the LNAs when operating in the bypass mode. This is performed by decoupling the active devices from ground to put the amplifying devices in a floating state, thus minimizing the impact of the gate-source capacitances of the amplifying devices on the overall linear performance of the LNA operating in the bypass mode.

Abstract: The present disclosure provides an integrated rice-crayfish-oriental river prawn planting-breeding method. The method includes the following steps: stocking crayfish postlarvae in a paddy field as an integrated rice-crayfish-oriental river prawn farming area from February to March, catching and marketing the crayfish from May to June; planting in mid-June, sun-drying rice seedlings in the field in late June, cleaning and disinfecting a ring ditch surrounding the paddy field, and transplanting some aquatic plants; stocking oriental river prawn postlarvae in early July; harvesting ripe rice in late October; and catching and marketing the oriental river prawns in November. On the premise that the rice planting area is not reduced, the present disclosure realizes the effective expansion of time and space of the paddy field and improves comprehensive benefits of rice-fish farming in the form of integrated rice-crayfish-oriental river prawn planting-breeding.

Abstract: The present application belongs to the technical field of research and development of fermented beverages, and a method for preparing Cordyceps militaris ferment by two-stage fermentation and complex enzymatic hydrolysis is provided. The present application involves preparation of a Cordyceps militaris powder and a Cordyceps militaris slurry, preparation of a Cordyceps militaris fermentation substrate, lactic acid bacteria fermentation in combination with complex enzymatic hydrolysis, and yeast fermentation, followed by centrifugation, filtration, formulation, sterilization, and filling to obtain a product. By employing lactic acid bacteria fermentation in combination with complex enzymatic hydrolysis, and secondary fermentation by yeast, the present application can quickly finish a whole fermentation process in 2 to 3 days.

Abstract: Disclosed is an ultrasonic composite acidic water extraction method for a Cordyceps polysaccharide and cordycepin in Cordyceps militaris, which falls within the technical field of food processing. The method comprises: picking, washing, drying, pulverizing and degreasing Cordyceps militaris fruiting bodies to obtain a Cordyceps militaris dry powder; then immersing same in a prepared diluted hydrochloric acid solution to perform three cycles of ultra-low temperature freezing and microwave defrosting, and at the same time using low-frequency ultrasonic waves to carry out assisted stirring and extraction; then subjecting an extract to evaporation and concentration treatments; and finally, performing freeze-drying on the extract to collect a dry powder of a water extraction product.

Abstract: The invention discloses a method for preparing an amplicon library for detecting a low-frequency mutation of a target gene. The invention provides a method for preparing an amplicon library for detecting a low-frequency mutation of a target gene, comprising the following steps: 1) design and synthesize a Barcode primer F1, an forward primer F2, a reverse outer primer R1, and a reverse inner primer R2; 2) perform a one-step PCR amplification on the cfDNA of the sample to be tested using the Barcode primer F1, the forward primer F2, the reverse outer primer R1, and the reverse inner primer R2 to obtain an amplified product, which is a DNA library for an amplicon sequencing. In addition to detect tissue samples, the method can also quickly, easily, sensitively and specifically amplify different target regions of cell free DNA from samples such as blood, urine, and CSF, and efficiently detect mutations as low as 0.1%.

Abstract: Provided is a method for performing layer Q factor inversion by using an amplitude spectrum attribute of a down going wave of vertical seismic profile data in a geophysical exploration data processing technology. In the method, first an F-K (frequency-wave number) method is used to perform wave field separation on VSP original data, so as to obtain a down going wave; a down going wavelet and a monitoring wavelet are selected to undergone Fourier transform to obtain an amplitude spectrum, polynomial fitting is performed on the amplitude spectrum to obtain an equivalent Q, and a formula between the equivalent Q and a layer Q is used to perform inversion, so as to obtain the layer Q. The method has a strong capability of resisting random disturbance, and is capable of removing a difference of triggering wavelet. The algorithm is simple and can greatly save workload; moreover, the layer Q value obtained through inversion has a desirable stability and high precision.

Abstract: A method for operating an N-bit SAR ADC as a greater than N-bit resolution SAR ADC includes the steps of taking a plurality of samples for each analog value being converted to a digital value by the SAR ADC. A portion of an LSB is added to all but one of the plurality of samples. The plurality of samples are then accumulated and output as a digital value. The digital value has a resolution greater than the N-bit resolution of the SAR ADC.

Abstract: A microcontroller includes a processing unit having a processing unit having normal power mode of operation and a low power mode of operation. The processing unit further having digital circuitry connected to the processing unit having a plurality of logic circuits associated therewith for processing digital values. A plurality of retention flip-flops are associated with the digital circuitry for storing a logical state of at least one or more of the logic circuits within the digital circuitry when the processing unit enters the low power mode of operation. The plurality of retention flip flops include a first type of transistors for operating in both the low and high power modes of operation and a second type of transistors for operation only in the normal mode of operation and wherein substantially the remainder of the digital circuitry in the processing unit comprises the second type of transistors.

Abstract: The single chip microcontroller unit includes a processing unit having normal power mode of operation and a low power mode of operation. Analog circuitry and digital circuitry are connected to the processing unit. Monitoring circuitry determines if a chip supply voltage level exceeds a threshold level necessary to maintain operation of the digital circuitry.

Abstract: The single chip microcontroller unit includes a processing unit having normal power mode of operation and a low power mode of operation. Analog circuitry and digital circuitry are connected to the processing unit. A power management unit controls power operations of the processing unit, the analog circuitry and the digital circuitry. Power monitoring circuitry provides power control signals to the power management unit. The power monitoring circuitry further includes a system voltage monitoring circuit for generating a system voltage control signal responsive to a system voltage level with respect to a predetermined level. The power monitoring circuitry also includes a supply monitoring circuit for determining if a chip supply voltage level exceeds a threshold level.

Abstract: A successive approximation analog-to-digital converter includes a capacitor array having a plurality of switch capacitors therein with varying weights, each having a common plate connected to a common node and a switched plate. A SAR controller samples an input voltage on said capacitor array in a sampling phase and redistributes the charge stored therein in a conversion phase by selectively increasing the voltage on select capacitors of the capacitor array in accordance with a SAR conversion algorithm. Circuitry controls the sampling of the input voltage by the capacitor array and is responsive to at least one applied bias current. The at least one applied bias current operates at a first level responsive to a first mode of operation of the SAR ADC and operates at a second level responsive to a second mode of operation of the SAR ADC.

Abstract: A successive approximation analog-to-digital converter includes a capacitor array having a plurality of switch capacitors therein with varying weights, each having a common plate connected to a common node and a switched plate. A SAR controller samples an input voltage on said capacitor array in a sampling phase and redistributes the charge stored therein in a conversion phase by selectively increasing the voltage on select capacitors of the capacitor array in accordance with a SAR conversion algorithm. Circuitry controls the sampling of the input voltage by the capacitor array and is responsive to at least one applied bias current. The at least one applied bias current operates at a first level responsive to a first mode of operation of the SAR ADC and operates at a second level responsive to a second mode of operation of the SARADC.

Abstract: A method for operating an N-bit SAR ADC as a greater than N-bit resolution SAR ADC includes the steps of taking a plurality of samples for each analog value being converted to a digital value by the SAR ADC. A portion of an LSB is added to all but one of the plurality of samples. The plurality of samples are then accumulated and output as a digital value. The digital value has a resolution greater than the N-bit resolution of the SAR ADC.

Abstract: The integrated circuit package includes a processing core for operating on a set of instructions to carry out predefined processes. A real time clock circuit provides a system clock for the processing core. The real time clock further comprises an internal oscillator that generates the system clock for the integrated circuit package. The internal oscillator has a factory calibrated bias current. An internal oscillator control register controls the operation of the internal oscillator responsive to control bits of the programmable load capacitor array controlled by the processing core.

Abstract: The single chip microcontroller unit includes a processing unit having normal power mode of operation and a low power mode of operation. Analog circuitry and digital circuitry are connected to the processing unit. Monitoring circuitry determines if a chip supply voltage level exceeds a threshold level necessary to maintain operation of the digital circuitry.

Abstract: The single chip microcontroller unit includes a processing unit having normal power mode of operation and a low power mode of operation. Analog circuitry and digital circuitry are connected to the processing unit. A power management unit controls power operations of the processing unit, the analog circuitry and the digital circuitry. Power monitoring circuitry provides power control signals to the power management unit. The power monitoring circuitry further includes a system voltage monitoring circuit for generating a system voltage control signal responsive to a system voltage level with respect to a predetermined level. The power monitoring circuitry also includes a supply monitoring circuit for determining if a chip supply voltage level exceeds a threshold level.

Abstract: The integrated circuit package includes a processing core for operating on a set of instructions to carry out predefined processes. An internal oscillator provides a system clock for the integrated circuit package. A programmable load capacitor array provides a programmable load to tune an oscillation frequency of the internal oscillator. An internal oscillator control register for controlling the operation of the programmable load capacitor array responsive to control bits of the programmable load capacitor array controlled by the processing core.

Abstract: The integrated circuit package includes a processing core for operating on a set of instructions to carry out predefined processes. A real time clock circuit provides a system clock for the processing core. The real time clock further comprises an internal oscillator that generates the system clock for the integrated circuit package. The internal oscillator has a factory calibrated bias current. An internal oscillator control register controls the operation of the internal oscillator responsive to control bits of the programmable load capacitor array controlled by the processing core.

Abstract: A microcontroller includes a processing unit having a processing unit having normal power mode of operation and a low power mode of operation. The processing unit further having digital circuitry connected to the processing unit having a plurality of logic circuits associated therewith for processing digital values. A plurality of retention flip-flops are associated with the digital circuitry for storing a logical state of at least one or more of the logic circuits within the digital circuitry when the processing unit enters the low power mode of operation. The plurality of retention flip flops include a first type of transistors for operating in both the low and high power modes of operation and a second type of transistors for operation only in the normal mode of operation and wherein substantially the remainder of the digital circuitry in the processing unit comprises the second type of transistors.