Abstract: Processor-based systems employing configurable local frequency throttling management to manage power demand and consumption, and related methods. For example, such processor-based systems may include a processor and other power circuitry to control power to the processor. The processor includes a clock control circuit that is configured generate a clock signal(s) at a designated frequency to clock a processor core(s) in the processor at a desired operating frequency(ies). The clock control circuit is configured to dynamically throttle (i.e., limit and/or reduce) the frequency(ies) of a clock signal(s) clocking the processor in response to a frequency throttle event that may be an unexpected event. Reducing power demand may be important to ensure that the processor can continue to operate under interrupted or reduced power supply conditions. It may be faster to throttle the operating frequency of a processor than to throttle the operating voltage of power supplied to the processor.

Abstract: A computing device including a hardware accelerator. The hardware accelerator includes a generalized matrix-vector multiplication (GEMV) circuit configured to compute a product vector over a plurality of streaming iterations. At each of the streaming iterations, the GEMV circuit receives an input vector element and an input matrix row. The GEMV circuit multiplies the input vector element by input matrix elements included in the input matrix row to obtain an intermediate product row. The GEMV circuit adds the intermediate product row to a current-iteration row sum. The product vector is equal to the current-iteration row sum computed in a final streaming iteration. The GEMV circuit transmits the product vector as a streaming output to a post-processing circuit included in the hardware accelerator. The post-processing circuit performs a vector processing operation on the product vector to compute vector processing result, and outputs the vector processing result.

Abstract: The description relates to dynamic memory management. One example includes an assembly that entails processing elements and memory. A dynamic UMA/NUMA configuration module is configured to facilitate managing a first region of the memory based upon a Uniform Memory Access (UMA) architecture and a second region of the memory based upon a Non-Uniform Memory Access (NUMA) architecture. The dynamic UMA/NUMA configuration module is configured to dynamically adjust ratios of the memory in the first region and the second region based upon workload changes on the processing elements.

Abstract: A method for computer workload allocation at a system-on-chip (SoC) includes, at a load balancing controller of the SoC, dividing a computer workload for distributed processing between each of a plurality of hardware accelerators of the SoC as a plurality of accelerator-specific data allocations. At a hardware accelerator of the plurality of hardware accelerators, after receiving an accelerator-specific data allocation from the load balancing controller, a resulting dataset output by the hardware accelerator is divided between a plurality of network interface controllers (NICs) of the SoC as a plurality of NIC-specific data allocations. At an NIC of the plurality of NICs an NIC-specific data allocation assigned to the NIC is divided between a plurality of network ports of the NIC for transmission over a computer network.

Abstract: A method for a hardware thread allocation controller of a computing device includes receiving, at the hardware thread allocation controller, a processor thread including one or more processing commands to be executed, and one or more preconditions for execution of the processor thread. The processor thread is stored in a thread queue of the hardware thread allocation controller. Based at least in part on detecting that the one or more preconditions for execution are met, the processor thread is assigned to a hardware accelerator of the computing device for execution, wherein the hardware thread allocation controller is configured to receive the processor thread, store the processor thread in the thread queue, and assign the processor thread to the hardware accelerator through hardware programming of the hardware thread allocation controller.

Abstract: Examples of the present disclosure describe devices, systems, and methods for runtime profiling workload on a system on a chip (SOC). In examples. A SOC records runtime metrics while running a workload using counters to calculate the usage of logical partitions of the SOC. The SOC uses the runtime metrics to determine the logical partitions' performance characteristics and the processors' optimal clock frequency in each logical partition based on the performance characteristics. The SOC sets the clock speeds of a processor in a logical partition while the workload is still running on the SOC to its optimal clock frequency.

Abstract: A computing device including memory storing a mixed-precision tensor. The mixed-precision tensor includes one or more first tensor regions within which first tensor elements have a first precision and one or more second tensor regions within which second tensor elements have a second precision. The memory further stores a precision map indicating the first and second tensor regions. The computing device further includes a hardware accelerator configured to receive the precision map and the one or more first tensor regions, as indicated by the precision map, and perform a tensor processing operation on the one or more first tensor regions in the first precision. The hardware accelerator receives the one or more second tensor regions, as indicated by the precision map, and performs the tensor processing operation on the one or more second tensor regions in the second precision. The hardware accelerator stores a combined tensor processing output.

Abstract: An activity smoothener circuit is provided to control rates of change in processing activity to limit di/dt in activity areas of an IC to mitigate voltage droops or overshoots. Controlling the rate of change of activity prevents or reduces instances of a di/dt exceeding a programmed maximum that is based on physical limits of the IC and/or a package. In examples, the activity smoothener circuit includes a hierarchy of smoothening circuits controlling activity in areas down to individual circuit blocks (tiles) including execution circuits. An indication of a desired level of activity is provided to a parent smoothening circuit and the parent smoothening circuit responds with indications of actual activity allowed to occur. At each level of hierarchy, the activity smoothener circuit may use algorithms to generate indications of actual activity based on indications of desired activity and di/dt limits. Di/dt limits and current minimums and maximums are controlled.

Abstract: A computing device is provided, including a plurality of memory devices, a plurality of direct memory access (DMA) controllers, and an on-chip interconnect. The on-chip interconnect may be configured to implement control logic to convey a read request from a primary DMA controller of the plurality of DMA controllers to a source memory device of the plurality of memory devices. The on-chip interconnect may be further configured to implement the control logic to convey a read response from the source memory device to the primary DMA controller and one or more secondary DMA controllers of the plurality of DMA controllers.

Abstract: Homogeneous chiplets configurable both as a two-dimensional system or a three-dimensional system are described. An example chiplet system has a first homogeneous chiplet (HC) including a first integrated circuit (IC) die having a first logic block and a first memory that are interconnected via a first path for transfer of data signals between the first logic block and the first memory block. A second HC including a second IC die having a second logic block and a second memory block, interconnected via a second path for transfer of data signals between the second logic block and the second memory block, is stacked vertically on top of the first HC to provide a third path for transfer of data signals between the first logic block and the second memory block and a fourth path for transfer of data signals between the second logic block and the first memory block.

Abstract: Homogeneous chiplets configurable both as a two-dimensional system or a three-dimensional system are described. An example chiplet system has a first homogeneous chiplet (HC) including a first integrated circuit (IC) die having a first logic block and a first memory that are interconnected via a first path for transfer of data signals between the first logic block and the first memory block. A second HC including a second IC die having a second logic block and a second memory block, interconnected via a second path for transfer of data signals between the second logic block and the second memory block, is stacked vertically on top of the first HC to provide a third path for transfer of data signals between the first logic block and the second memory block and a fourth path for transfer of data signals between the second logic block and the first memory block.

Abstract: An activity smoothener circuit is provided to control rates of change in processing activity to limit di/dt in activity areas of an IC to mitigate voltage droops or overshoots. Controlling the rate of change of activity prevents or reduces instances of a di/dt exceeding a programmed maximum that is based on physical limits of the IC and/or a package. In examples, the activity smoothener circuit includes a hierarchy of smoothening circuits controlling activity in areas down to individual circuit blocks (tiles) including execution circuits. An indication of a desired level of activity is provided to a parent smoothening circuit and the parent smoothening circuit responds with indications of actual activity allowed to occur. At each level of hierarchy, the activity smoothener circuit may use algorithms to generate indications of actual activity based on indications of desired activity and di/dt limits. Di/dt limits and current minimums and maximums are controlled.

Abstract: The present disclosure relates to systems, methods, and computer-readable media for data from a first multi-dimensional memory block to a second multi-dimensional memory block. For example, systems described herein facilitate transferring data between memory blocks having different shapes from one another. The systems described herein facilitate transferring data between different shaped memory blocks by identifying shape properties and other characteristics of the data and generating a plurality of network packets having control data based on the identified shape properties and other characteristics. This data included within the network packets enables memory controllers to determine memory addresses on a destination memory block to write data from the network packets. Features described herein facilitate efficient transfer of data without generating a linearized copy that relies on constant availability of significant memory resources.

Abstract: A computing device is provided, including a plurality of memory devices, a plurality of direct memory access (DMA) controllers, and an on-chip interconnect. The on-chip interconnect may be configured to implement control logic to convey a read request from a primary DMA controller of the plurality of DMA controllers to a source memory device of the plurality of memory devices. The on-chip interconnect may be further configured to implement the control logic to convey a read response from the source memory device to the primary DMA controller and one or more secondary DMA controllers of the plurality of DMA controllers.

Abstract: A method for manufacturing a side wire for a substrate and a substrate structure are provided. The method includes: forming a plurality of first pattern structures on a side surface of the substrate, wherein a gap between any adjacent two of the plurality of first pattern structures connects a top surface and a bottom surface of the substrate to each other; forming a conductive material film covering the side surface of the substrate; and removing the plurality of first pattern structures and a portion of the conductive material film that is attached on the plurality of first pattern structures, and maintaining a portion of the conductive material film that is located between any adjacent two of the plurality of first pattern structures as the side wire.

Abstract: A computing device is provided, including a plurality of memory devices, a plurality of direct memory access (DMA) controllers, and an on-chip interconnect. The on-chip interconnect may be configured to implement control logic to convey a read request from a primary DMA controller of the plurality of DMA controllers to a source memory device of the plurality of memory devices. The on-chip interconnect may be further configured to implement the control logic to convey a read response from the source memory device to the primary DMA controller and one or more secondary DMA controllers of the plurality of DMA controllers.

Abstract: An activity smoothener circuit is provided to control rates of change in processing activity to limit di/dt in activity areas of an IC to mitigate voltage droops or overshoots. Controlling the rate of change of activity prevents or reduces instances of a di/dt exceeding a programmed maximum that is based on physical limits of the IC and/or a package. In examples, the activity smoothener circuit includes a hierarchy of smoothening circuits controlling activity in areas down to individual circuit blocks (tiles) including execution circuits. An indication of a desired level of activity is provided to a parent smoothening circuit and the parent smoothening circuit responds with indications of actual activity allowed to occur. At each level of hierarchy, the activity smoothener circuit may use algorithms to generate indications of actual activity based on indications of desired activity and di/dt limits. Di/dt limits and current minimums and maximums are controlled.

Abstract: Processor-based systems employing configurable local frequency throttling management to manage power demand and consumption, and related methods. For example, such processor-based systems may include a processor and other power circuitry to control power to the processor. The processor includes a clock control circuit that is configured generate a clock signal(s) at a designated frequency to clock a processor core(s) in the processor at a desired operating frequency(ies). The clock control circuit is configured to dynamically throttle (i.e., limit and/or reduce) the frequency(ies) of a clock signal(s) clocking the processor in response to a frequency throttle event that may be an unexpected event. Reducing power demand may be important to ensure that the processor can continue to operate under interrupted or reduced power supply conditions. It may be faster to throttle the operating frequency of a processor than to throttle the operating voltage of power supplied to the processor.

Abstract: Disclosed are a near-eye display device and a near-eye display system. The excitation light source structure provides excitation light to the first waveguide structure, and the outgoing coupling grating structure corresponding to the first waveguide structure receiving the excitation light may be further irradiated by the excitation light, and be excited and output the light with a pixel color corresponding to the first waveguide structure. That is, the outgoing coupling grating structure corresponding to the first waveguide structure receiving the excitation light can derive the light with the corresponding pixel color emitted by the projection-based display, and be excited by the excitation light emitted by the excitation light source structure to output light with a pixel color corresponding to the first waveguide structure.