Abstract: A mask includes: a transparent substrate; and a light-shielding layer provided on one side of the transparent substrate, and including a first conductive pattern, a second conductive pattern, and an electrostatic discharge line, wherein a hollow-out area is provided between the first conductive pattern and the second conductive pattern, and the electrostatic discharge line is positioned in the hollow-out area; and one side of the first conductive pattern facing the second conductive pattern includes a first edge and a second edge, the first edge and the second edge are connected to form a first concave angle, a first end of the electrostatic discharge line is electrically connected to the first concave angle, and a second end of the electrostatic discharge line is electrically connected to the second conductive pattern.

Abstract: The present disclosure provides a display panel. The display panel includes a first substrate and a second substrate. The display panel includes a display area and a non-display area, at least one mark area is arranged in the non-display area, each mark area includes at least one assembling mark group, each assembling mark group is configured to detect an assembling deviation in a preset direction and includes: a first assembling mark arranged on a side of the first substrate close to the second substrate and in a comb shape, and a second assembling mark arranged on a side of the second substrate close to the first substrate and in the comb shape, comb teeth of the first assembling mark face the second assembling mark, comb teeth of the second assembling mark face the first assembling mark, and a length direction of the comb teeth is perpendicular to the preset direction.

Abstract: A display substrate includes a driving circuit arranged on a base substrate, the driving circuit includes a first node control circuit including a first transistor and a second transistor; a gate/first/second electrode of the first transistor is electrically connected to a first control terminal/a first voltage terminal/the first node; a gate/first/second electrode of the second transistor is electrically connected to a second control terminal/the first node/a second voltage terminal; the display substrate also includes a first connection structure and a second connection structure arranged on the base substrate; the first transistor is connected to a part of the first connection structure; and/or, the second transistor is connected to a part of the second connection structure.

Abstract: A display panel includes a display area and a peripheral area. The peripheral area includes a first signal line arrangement region including first signal lines and a second signal line arrangement region including second signal lines. First lead-out lines are led out from the first lead-out positions included in a border of the first signal line arrangement region and are connected to the first signal lines. A first lead-out line is connected to a data line. A first reference signal line is led out from a first reference lead-out position and connected to a first reference data line. Second lead-out lines are led out from second lead-out positions included in a border of the second signal line arrangement region, and are electrically connected to the second signal lines; a second lead-out line is electrically connected to a gate line.

Abstract: A display panel includes a display region and a peripheral region surrounding the display region, and the peripheral region includes a first region, a second region, a third region and a fourth region; and the second region includes a bonding region. The display panel includes a light-sensing unit and bonding electrodes. The light-sensing unit includes a light-shielding unit and a light leakage unity; the light-shielding unit includes light-shielding transistors, and the light leakage unit includes light leakage transistors; and the light-sensing unit is arranged in at least one of the first region, the second region, the third region and the fourth region. The bonding electrodes are disposed in the bonding region of the display panel, and the bonding electrodes are configured to be connected to a dimming chip.

Abstract: A display substrate includes a driving circuit arranged on a base substrate, the driving circuit includes a first node control circuit including a first transistor and a second transistor; a gate/first/second electrode of the first transistor is electrically connected to a first control terminal/a first voltage terminal/the first node; a gate/first/second electrode of the second transistor is electrically connected to a second control terminal/the first node/a second voltage terminal; the display substrate also includes a first connection structure and a second connection structure arranged on the base substrate; the first transistor is connected to a part of the first connection structure; and/or, the second transistor is connected to a part of the second connection structure.

Abstract: A display panel includes a display area and a peripheral area. The peripheral area includes a first signal line arrangement region including first signal lines and a second signal line arrangement region including second signal lines. First lead-out lines are led out from the first lead-out positions included in a border of the first signal line arrangement region and are connected to the first signal lines. A first lead-out line is connected to a data line. A first reference signal line is led out from a first reference lead-out position and connected to a first reference data line. Second lead-out lines are led out from second lead-out positions included in a border of the second signal line arrangement region, and are electrically connected to the second signal lines; and second lead-out line is electrically connected to a gate line.

Abstract: The present invention provides a method for preparing 3C-SiC single crystals, comprising the steps of: (1) fixing a SiC seed crystal to a graphite seed crystal holder, and then fixing the graphite seed crystal holder to a graphite lifting rod; (2) placing a flux containing Si and Al in a graphite crucible; (3) then loading the graphite crucible and the graphite lifting rod into a growth furnace; (4) vacuumizing the growth furnace, and then introducing a gas to control the gas pressure in the growth furnace and the crystal form of 3C-SiC; (5) heating the graphite crucible until the flux is completely molten to form a melt, and reaches the growth temperature of SiC, (6) pushing down the graphite lifting rod to make the SiC seed crystals contact with the melt, thereby growing 3C-SiC single crystals; wherein the flux further contains a 3d-transition metal with a melting point lower than the growth temperature of SiC.

Abstract: Provided is a method for manufacturing a trench capacitor. The method includes the steps as follows. A substrate is provided, where the substrate has a first trench. A first electrode layer is formed in the first trench, where the first electrode layer covers the first trench and a surface of the substrate. A first dielectric layer is formed, where the first dielectric layer covers the first electrode layer. A second dielectric layer is formed, where the second dielectric layer covers at least the first dielectric layer on the surface of the substrate, and the second dielectric layer has a thickness greater than that of the first dielectric layer. A second electrode layer is formed on the second dielectric layer, where the second electrode layer covers the second dielectric layer. A third dielectric layer is formed, where the third dielectric layer fills the remaining first trench.

Abstract: A display substrate, manufacturing method thereof, and a display device. The display substrate includes a base substrate and a semiconductor layer and a conductive layer on the base substrate. The semiconductor layer includes a channel region and a doped region pattern of a transistor; the conductive layer includes a data line, and a first electrode and a second electrode of the transistor. An extension direction of an overlapping portion of the semiconductor layer with the data line is the same as an extension direction of the data line, and the semiconductor layer includes a first protrusion portion, and a size of an interval between an edge of the first protrusion portion away from the data line and the edge of the data line is greater than 0 and smaller than 3.0 microns.

Abstract: The present invention discloses a conductive silver aluminum paste, a preparation method, an electrode, and an N-type Topcon battery. The conductive silver aluminum paste comprises silver powder, metal powder containing aluminum element, powder containing silicon or boron element, glass powder, and organic carrier; wherein, when defining the total weight of the conductive silver aluminum paste as 100%, the weight percentage content of each component is: silver powder 80.0%-90.0%, metal powder containing aluminum element 0.5%-3.0%; powder containing silicon or boron element 0.1%-1.0%; glass powder 1.5%-6.0%; organic carrier 7.0%-15.0%. The present invention meets requirements for electrode materials of current development of N-type Topcon batteries well, and has advantages of low contact resistances, high open circuit voltages, high photoelectric conversion efficiency, and high output power.

Abstract: A tetrahydrofolate methyltransferase mutant, its encoding gene, and applications thereof are provided. The amino acid sequence of a tetrahydrofolate methyltransferase RcoDmdA mutant is as shown in SEQ ID NO: 3. The RcoDmdA mutant possesses higher catalytic activity, allows the substrate THF feeding amount to be significantly increased to 15-20 g/L, increases the product L-5-MTHF yield to 15-17 g/L, and has high substrate conversion rate. The tetrahydrofolate methyltransferase mutant and its encoding gene have important industrial application value.

Abstract: An antibody-conjugated liposome, particularly a nanoparticle. The surface of the nanoparticle contains antibodies. The number of the antibodies is 5-60, preferably 5-50, and more preferably 5-40. The nanoparticle, for example, a liposome, can more effectively exert a therapeutic effect on tumor and improve multidrug resistance of tumor, thereby overcoming the technical prejudice that it is commonly considered that the more antibodies on a surface of a liposome, the better the target cell binding effect, and laying a foundation for further clinical development. An antibody-conjugated liposome, particularly a nanoparticle, the surface of which contains antibodies, and the number of the antibodies is 5-60, preferably 5-50, and more preferably 5-40. The nanoparticle, such as a liposome, can more effectively exert a therapeutic effect on tumors and reduce the multidrug resistance of tumors.

Abstract: A display panel includes a display area and a peripheral area. The peripheral area includes a first signal line arrangement region including first signal lines and a second signal line arrangement region including second signal lines. First lead-out lines are led out from the first lead-out positions included in a border of the first signal line arrangement region and a are connected to the first signal lines. A first lead-out line is connected to a data line. A first reference signal line is led out from a first reference lead-out position and connected to a first reference data line. Second lead-out lines are led out from second lead-out positions included in a border of the second signal line arrangement region, and are electrically connected to the second signal lines; a second lead-out line is electrically connected to a gate line.

Abstract: This application discloses a network fault analysis method and apparatus. The method includes: obtaining information about a first abnormal event and information about a second abnormal event; determining first fault cause description information and second fault cause description information respectively based on the information about the first abnormal event and the information about the second abnormal event, where each of the first and the second fault cause description information is used to describe a cause of occurrence of a corresponding abnormal event; and determining, based on event identifiers in the information about the first and the second abnormal events, and the first and the second fault cause description information, that the first abnormal event corresponding to the first fault cause description information is a cause event that causes occurrence of the second abnormal event corresponding to the second fault cause description information.

Abstract: A driver module includes a first driver unit and a first control unit; the first driver unit includes M levels of first driver circuits; M is a positive integer; m is a positive integer less than or equal to M; the m-th level first drive signal output terminal is electrically connected to a first terminal of an m-th row first gate line, to provide an m-th level first drive signal to the m-th row first gate line; the first control unit includes M first control circuits; an m-th first control circuit included in the first control unit is electrically connected to a second terminal of the m-th row first gate line, configured to control the second terminal of the m-th row first gate line to receive an ineffective voltage signal when a voltage value of the m-th level first drive signal changes from an effective voltage to an ineffective voltage.

Abstract: The present invention discloses conductive silver paste for sintering by LECO technology, a preparation method, an electrode, and a battery. The conductive silver paste comprises silver powder, glass powder, organic carrier, and inorganic additive; in weight percentage, the weight percentage contents of these components are: silver powder 84.0%-92.0%, glass powder 0.5%-3.0%; organic carrier 6.5%-13.5%; inorganic additive 0.2%-1.0%; wherein the glass powder comprises main glass powder, the main glass powder is glass powder containing Pb, O, and first main element, second main element, and third main element systems; the first main element comprises at least Si, the second main element comprises at least B, the third main element comprises at least Ag. An N-type TOPcon battery manufactured by the conductive silver paste of the present invention has characteristics of a high opening voltage and high photoelectric conversion efficiency.

Abstract: A driver module includes a first driver unit and a first control unit; the first driver unit includes M levels of first driver circuits; M is a positive integer; m is a positive integer less than or equal to M; the m-th level first drive signal output terminal is electrically connected to a first terminal of an m-th row first gate line, to provide an m-th level first drive signal to the m-th row first gate line; the first control unit includes M first control circuits; an m-th first control circuit included in the first control unit is electrically connected to a second terminal of the m-th row first gate line, configured to control the second terminal of the m-th row first gate line to receive an ineffective voltage signal when a voltage value of the m-th level first drive signal changes from an effective voltage to an ineffective voltage.

Abstract: The present disclosure relates to an all-trans retinoic acid liposome formulation and a preparation method thereof. The all-trans retinoic acid liposome formulation includes all-trans retinoic acid and a liposome vector. The disclosure adopts an active drug loading method, including a calcium acetate gradient method or a sodium acetate gradient method. The prepared all-trans retinoic acid formulation has high drug loading and high stability in vivo, thereby increasing the blood concentration and prolonging the half-life of the all-trans retinoic acid.

Abstract: A thermal barrier coating (TBC) material with high fracture toughness, calcia-magnesia-alumino silicate (CMAS) corrosion resistance, and ultra-high-temperature sintering resistance, and a preparation and use thereof are provided, belonging to the technical field of high-temperature/ultra-high-temperature TBCs. In the TBC material, ZrO2 is co-doped with different rare earth oxides and a crystal defect concentration and a lattice distortion degree are controlled by a doping amount of the rare earth oxides, resulting in a fully-stabilized cubic fluorite crystal structure showing no phase change at a room temperature to 1,600° C. Moreover, the material exhibits high toughness, CMAS corrosion resistance, ultra-high-temperature sintering resistance, and long service life.