Abstract: A display panel and a driving method thereof are provided. The driving method includes: acquiring a display synchronization signal, and according to it to determine a first backlight synchronization signal including a plurality of second pulses corresponding to a plurality of first pulses in the display synchronization signal; acquiring a display setting frequency greater than a minimum value of refresh rates of frame images, and according to it to determine a unit backlight clock signal, where a duration of the unit backlight clock signal is equal to of a reciprocal of the display setting frequency; and generating a third pulse between some two adjacent second pulses to drive a backlight plate to emit light.

Abstract: The present invention provides a thermally conductive silicone composition comprising: (A) at least one alkenyl group-containing organopolysiloxane; (B) at least one organohydrogenpolysiloxane having at least two hydrogen atoms directly bonded to a silicon atom in the molecule; (C1) one or more silane surface-treated alumina particles having a D50 particle size of at least 0.01 ?m but no greater than 5 ?m; (C2) one or more silane surface-treated alumina particles having a D50 particle size of greater than 5 ?m; (D) at least one silane coupling agent; and (E) at least one platinum-based curing catalyst; wherein component (C1) is present in an amount of less than 62% by weight based on the weight of the composition and the component (C2) is present in an amount of less than 80% by weight based on the weight of the composition, which features favorable combination of properties including good flowability, as well as high thermal conductivity and good lap shear strength when cured.

Abstract: This application provides a calibration device and a method. The calibration device includes calibration boards arranged at intervals and having board surface parallel to each other, a guide rail disposed at peripheries of the calibration boards, TOF cameras, and a controller. Support frames are arranged at intervals on the guide rail, and the TOF cameras are mounted on the guide rail using the support frames. Distances between the calibration surfaces and the corresponding TOF cameras are different. The controller is connected to the guide rail and the TOF cameras, and configured to send a first set of timing control signals to control the guide rail to carry the TOF cameras to move along the guide rail, and send a second set of timing control signals to the TOF cameras to control the TOF cameras to work simultaneously or alternately to measure distance values between the TOF cameras and the corresponding calibration boards.

Abstract: The present invention discloses a superconducting nanowire single photon detector, comprises an arced fractal nanowire structure and the optical cavity structure; the arced fractal nanowire structures being used to alleviate the current-crowding effect and realize that the detection efficiency is insensitive to the polarization states of incident photons, and the arced fractal nanowire structures including parallel-connected arced fractal nanowires and serial-connected arced fractal nanowires; the optical cavity structure being used to achieve simultaneous optimization of the internal quantum efficiency and the absorption efficiency. The invention can be widely used in many fields such as optical communication, single-photon imaging, fluorescence detection, quantum optics, etc. The excellent performance of the detector can significantly promote the development and progress of these fields.

Abstract: A liquid crystal display apparatus is provided. The liquid crystal display apparatus comprises a backplane having a second step portion and a first step portion used for supporting a liquid crystal panel, that is, the assembly of optical parts such as a light homogenizing element and an optical film to the liquid crystal panel is implemented in the present application via the backplane without a middle frame.

Abstract: This application provides a calibration device and a method. The calibration device includes calibration boards arranged at intervals and having board surface parallel to each other, a guide rail disposed at peripheries of the calibration boards, TOF cameras, and a controller. Support frames are arranged at intervals on the guide rail, and the TOF cameras are mounted on the guide rail using the support frames. Distances between the calibration surfaces and the corresponding TOF cameras are different. The controller is connected to the guide rail and the TOF cameras, and configured to send a first set of timing control signals to control the guide rail to carry the TOF cameras to move along the guide rail, and send a second set of timing control signals to the TOF cameras to control the TOF cameras to work simultaneously or alternately to measure distance values between the TOF cameras and the corresponding calibration boards.

Abstract: Biological assay systems, methods, and devices for detecting the presence of the virus responsible for COVID-19 (sars-cov-2) in the saliva of an individual. The systems, methods, and devices utilize immunoassay technology for detecting the presence of antigen in a sample, such as the virus responsible for COVID-19 in the saliva of an individual. The immunoassay technology in accordance with embodiments of the systems, methods, and devices use nano-carbon, or carbon nanoparticles attached to biorecognition/detector molecules, such as antibodies.

Abstract: A time flight depth camera and a distance measuring method are provided. The time flight depth camera comprises: a light source for emitting a pulse beam to an object; an image sensor comprising at least one pixel, wherein each of the at least one pixel comprises taps, and each tap is used for acquiring a charge signal based on a reflected pulse beam due to the pulse beam reflected from the object to be measured or a charge signal of background light; and a processing circuit configured to control the light source to emit pulse beams in adjacent frame periods, receive charge signals of the taps in the adjacent frame periods, determine whether the charge signals comprise the charge signal of the reflected pulse beam, and calculate a time of flight of the pulse beam and/or a distance to the object according to a result of the determining.

Abstract: A preparation method for a metal-doped gallium oxide transparent conductive thin film for ultraviolet waveband includes: growing a contact layer thin film (2) on a substrate (1) first, and annealing the grown contact layer thin film (2) in a nitrogen-oxygen atmosphere at 400° C. to 600° C. through a rapid thermal annealing furnace; growing a first Ga2O3 thin film (31) by sputtering through magnetron sputtering under argon conditions; growing a doped thin film (4) by sputtering through magnetron sputtering under argon conditions; growing a second Ga2O3 thin film (32) by sputtering through magnetron sputtering under argon conditions; and annealing the grown thin films in a nitrogen-oxygen atmosphere at 500° C. to 600° C. through a rapid thermal annealing furnace, so that permeation, diffusion and fusion occur between thin film materials to form a metal-doped Ga2O3 thin film (5). A metal-doped gallium oxide transparent conductive thin film for ultraviolet waveband is provided.

Abstract: An efficient wide bandgap GaN-based LED chip based on a surface plasmon effect and a manufacturing method therefor. The efficient wide bandgap GaN-based LED chip is of a flip-chip structure, and comprises, from bottom to top in sequence, a substrate, a buffer layer, an unintentionally doped GaN layer, an n-GaN layer, a quantum well layer, an electron blocking layer, a p-GaN layer, a metallic reflecting mirror layer, a passivation layer, a p-electrode layer, an n-electrode layer; and a position of a bottom surface of the metallic reflecting mirror layer connected to a surface of the p-GaN layer is provided with a micro-nano composite metal structure. A micro metal structure comprises alternating protrusion portions and recess portions; and a nano metal structure is distributed on an interface of the micro metal structure and the p-GaN layer.

Abstract: A broadband efficient GaN-based LED chip based on a surface plasmon effect and a manufacturing method therefor. The broadband efficient GaN-based LED chip is of a flip-chip structure, and comprises, from bottom to top in sequence, a substrate, a buffer layer, an unintentionally doped GaN layer, an n-GaN layer, a quantum well layer, an electron blocking layer, a p-GaN layer, a metallic reflecting mirror layer, a passivation layer, a p-electrode layer, an n-electrode layer; and a position of a bottom surface of the metallic reflecting mirror layer connected to a surface of the p-GaN layer is provided with a micro-nano composite metal structure. A micro metal structure comprises alternating protrusion portions and recess portions; and a nano metal structure is distributed on an interface of the micro metal structure and the p-GaN layer.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. An insulating fill material layer and drain select gate electrodes are located over the alternating stack. A group of memory stack structures extends through the alternating stack, and is arranged as rows of memory stack structures. Each memory stack structure is entirely encircled laterally by a respective one of the drain select gate electrodes. The insulating fill material layer includes a drain select level isolation structure extending between neighboring rows of memory stack structures and including a pair of sidewalls containing a respective laterally alternating sequence of planar vertical sidewall portions and concave vertical sidewall portions, and a drain select level field portion adjoined to the drain select level isolation portion.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. An insulating fill material layer and drain select gate electrodes are located over the alternating stack. A group of memory stack structures extends through the alternating stack, and is arranged as rows of memory stack structures. Each memory stack structure is entirely encircled laterally by a respective one of the drain select gate electrodes. The insulating fill material layer includes a drain select level isolation structure extending between neighboring rows of memory stack structures and including a pair of sidewalls containing a respective laterally alternating sequence of planar vertical sidewall portions and concave vertical sidewall portions, and a drain select level field portion adjoined to the drain select level isolation portion.

Abstract: A three-dimensional memory device includes alternating stacks of insulating strips and electrically conductive strips located over a substrate and laterally spaced apart among one another by vertically undulating trenches. The vertically undulating trenches have a greater lateral extent at levels of the electrically conductive strips than at levels of the insulating strips. An interlaced two-dimensional array of memory stack assemblies and dielectric pillar structures are located in the vertically undulating trenches. Each memory stack assembly includes a vertical semiconductor channel and a pair of memory films including a respective pair of convex outer sidewalls that contact, or are spaced by a uniform distance from, concave sidewalls of the electrically conductive strips.

Abstract: A high voltage P-type lateral double-diffused metal oxide semiconductor field effect transistor (10) comprises: a substrate (100); an N-type lateral double-diffused metal oxide semiconductor field effect transistor (200) formed on the substrate (100); and a P-type metal oxide semiconductor field effect transistor (300) formed at a drain of the N-type lateral double-diffused metal oxide semiconductor field effect transistor (200); wherein a gate of the P-type metal oxide semiconductor field effect transistor (300) serves as a gate of the high voltage P-type lateral double-diffused metal oxide semiconductor field effect transistor (10); a drain of the P-type metal oxide semiconductor field effect transistor (300) serves as a drain of the high voltage P-type lateral double-diffused metal oxide semiconductor field effect transistor (10); a source of the N-type lateral double-diffused metal oxide semiconductor field effect transistor (200) serves as a source of the high voltage P-type lateral double-diffused metal

Abstract: An N type lateral double-diffused metal oxide semiconductor field effect transistor (200) includes a substrate (202); a first N well (204) formed on the substrate; a second N well (206), a first P well (208), a third N well (210) and a fourth N well (212); a source lead-out region (214) formed on the first P well (208); a drain lead-out region (216) formed on the fourth N well (212); a first gate lead-out region formed on surfaces of the second N well (206) and the first P well (208); and a second gate lead-out region formed on surfaces of the first P well (208) and the third N well (210). The first gate lead-out region and the second gate lead-out region are respectively led out by means of metal wires, and then are connected to serve as a gate.

Abstract: Flexible electronic structure and methods for fabricating flexible electronic structures are provided. An example method includes applying a first layer to a substrate, creating a plurality of vias through the first layer to the substrate, and applying a second polymer layer to the first layer such that the second polymer forms anchors contacting at least a portion of the substrate. At least one electronic device layer is disposed on a portion of the second polymer layer. At least one trench is formed through the second polymer layer to expose at least a portion of the first layer. At least a portion of the first layer is removed by exposing the structure to a selective etchant to providing a flexible electronic structure that is in contact with the substrate. The electronic structure can be released from the substrate.

Abstract: Techniques for forming 3D memory arrays are disclosed. Memory openings are filled with a sacrificial material, such as silicon or nitride. Afterwards, a replacement technique is used to remove nitride from an ONON stack and replace it with a conductive material such as tungsten. Afterwards, memory cell films are formed in the memory openings. The conductive material serves as control gates of the memory cells. The control gate will not suffer from corner rounding. ONON shrinkage is avoided, which will prevent control gate shrinkage. Block oxide between the charge storage region and control gate may be deposited after control gate replacement, so the uniformity is good. Block oxide may be deposited after control gate replacement, so TiN adjacent to control gates can be thicker to prevent fluorine attacking the insulator between adjacent control gates. Therefore, control gate to control gate shorting is prevented.

Abstract: The present invention provides a one part liquid underfill composition comprising an epoxy resin, a latent epoxy curing agent, a photocurable resin or monomer, a photoinitiator, an optional filler, and an optional thermal initiator. Also provided is a packaging process using the underfill composition.

Abstract: An alternating stack of insulator layers and spacer material layers is formed over a substrate. Stepped surfaces are formed in a contact region in which contact via structures are to be subsequently formed. An epitaxial semiconductor pedestal can be formed by a single epitaxial deposition process that is performed after formation of the stepped surfaces and prior to formation of memory openings, or a combination of a first epitaxial deposition process performed prior to formation of memory openings and a second epitaxial deposition process performed after formation of the memory openings. The epitaxial semiconductor pedestal can have a top surface that is located above a topmost surface of the alternating stack. The spacer material layers are formed as, or can be replaced with, electrically conductive layers. Backside contact via structures can be subsequently formed.