Patents by Inventor Xiaomei Bu
Xiaomei Bu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9054107Abstract: A method for forming a semiconductor device is presented. A substrate prepared with a dielectric layer formed thereon is provided. A sacrificial and a hard mask layer are formed on the dielectric layer. The dielectric, sacrificial and hard mask layers are patterned to form an interconnect opening. The interconnect opening is filled with a conductive material to form an interconnect. The conductive material is processed to produce a top surface of the conductive material that is substantially planar with a top surface of the sacrificial layer. The sacrificial layer is removed. The sacrificial layer protects the dielectric layer during processing of the conductive material.Type: GrantFiled: December 2, 2013Date of Patent: June 9, 2015Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Fan Zhang, Xiaomei Bu, Jane Hui, Tae Jong Lee, Liang Choo Hsia
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Publication number: 20140084486Abstract: A method for forming a semiconductor device is presented. A substrate prepared with a dielectric layer formed thereon is provided. A sacrificial and a hard mask layer are formed on the dielectric layer. The dielectric, sacrificial and hard mask layers are patterned to form an interconnect opening. The interconnect opening is filled with a conductive material to form an interconnect. The conductive material is processed to produce a top surface of the conductive material that is substantially planar with a top surface of the sacrificial layer. The sacrificial layer is removed. The sacrificial layer protects the dielectric layer during processing of the conductive material.Type: ApplicationFiled: December 2, 2013Publication date: March 27, 2014Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Fan ZHANG, Xiaomei BU, Jane HUI, Tae Jong LEE, Liang Choo HSIA
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Patent number: 8598031Abstract: A method for forming a semiconductor device is presented. A substrate prepared with a dielectric layer formed thereon is provided. A sacrificial and a hard mask layer are formed on the dielectric layer. The dielectric, sacrificial and hard mask layers are patterned to form an interconnect opening. The interconnect opening is filled with a conductive material to form an interconnect. The conductive material is processed to produce a top surface of the conductive material that is substantially planar with a top surface of the sacrificial layer. The sacrificial layer is removed. The sacrificial layer protects the dielectric layer during processing of the conductive material.Type: GrantFiled: September 28, 2009Date of Patent: December 3, 2013Assignee: Globalfoundries Singapore Pte. Ltd.Inventors: Fan Zhang, Xiaomei Bu, Jane Hui, Tae Jong Lee, Liang Choo Hsia
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Patent number: 7989338Abstract: Example embodiments of a structure and method for forming a copper interconnect having a doped region near a top surface. The doped region has implanted alloying elements that block grain boundaries and reduce stress and electro migration. In a first example embodiment, the barrier layer is left over the inter metal dielectric layer during the alloying element implant. The barrier layer is later removed with a planarization process. In a second example embodiment the barrier layer is removed before the alloying element implant and a hard mask blocks the alloying element from being implanted in the inter metal dielectric layer.Type: GrantFiled: June 15, 2005Date of Patent: August 2, 2011Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Fan Zhang, Kho Liep Chok, Alex See, Cheng-Cheh Tan, Xiaomei Bu, Tae Jong Lee, Liang Choo Hsia
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Publication number: 20110074039Abstract: A method for forming a semiconductor device is presented. A substrate prepared with a dielectric layer formed thereon is provided. A sacrificial and a hard mask layer are formed on the dielectric layer. The dielectric, sacrificial and hard mask layers are patterned to form an interconnect opening. The interconnect opening is filled with a conductive material to form an interconnect. The conductive material is processed to produce a top surface of the conductive material that is substantially planar with a top surface of the sacrificial layer. The sacrificial layer is removed. The sacrificial layer protects the dielectric layer during processing of the conductive material.Type: ApplicationFiled: September 28, 2009Publication date: March 31, 2011Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.Inventors: Fan ZHANG, Xiaomei BU, Jane HUI, Tae Jong LEE, Liang Choo HSIA
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Patent number: 7585768Abstract: A method of filling gaps in dielectric layers is disclosed. A wafer is provided having a dielectric layer containing gaps to be filled with copper, some of the gaps, denoted deeper gaps, having aspect ratios so large that filling these gaps with copper using ECP could result in pinhole like voids. A blanket conformal metal barrier layer is formed and the wafer is then submerged in a solution to electroless plate a blanket conformal copper seed layer. A partial filling of deeper gaps with copper reduces the effective aspect ratios of the deeper gaps to the extent that ECP could be used to complete the copper filling of the gaps without forming pinhole like voids. ECP is then used to complete the copper filling of the gaps. The wafer is annealed and CMP performed to planarize the surface, giving rise to a structure in which the gaps are filled with copper and are separated by the dielectric layer.Type: GrantFiled: June 16, 2006Date of Patent: September 8, 2009Assignee: Chartered Semiconductor Manufacturing, Ltd.Inventors: Xiaomei Bu, Alex See, Fan Zhang, Jane Hui, Tae Jong Lee, Liang Choo Hsia
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Publication number: 20070293039Abstract: A method of filling gaps in dielectric layers is disclosed. A wafer is provided having a dielectric layer containing gaps to be filled with copper, some of the gaps, denoted deeper gaps, having aspect ratios so large that filling these gaps with copper using ECP could result in pinhole like voids. A blanket conformal metal barrier layer is formed and the wafer is then submerged in a solution to electroless plate a blanket conformal copper seed layer. A partial filling of deeper gaps with copper reduces the effective aspect ratios of the deeper gaps to the extent that ECP could be used to complete the copper filling of the gaps without forming pinhole like voids. ECP is then used to complete the copper filling of the gaps. The wafer is annealed and CMP performed to planarize the surface, giving rise to a structure in which the gaps are filled with copper and are separated by the dielectric layer.Type: ApplicationFiled: June 16, 2006Publication date: December 20, 2007Inventors: Xiaomei Bu, Alex See, Fan Zhang, Jane Hui, Tae Jong Lee, Liang Choo Hsia
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Patent number: 7224060Abstract: A method of manufacturing an integrated circuit provides a substrate having a semiconductor device, and includes forming an intermetal dielectric layer over the substrate and the semiconductor device. A metal wire is formed above the semiconductor device and in contact therewith and a passivation layer is formed over the intermetal dielectric layer. A bond pad is formed connected to the metal wire. A protective moat, with sidewall passivation layer, is formed through the passivation layer and the intermetal dielectric layer, and is located between the metal wire and an outside edge of the integrated circuit.Type: GrantFiled: January 30, 2004Date of Patent: May 29, 2007Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Fan Zhang, Kho Liep Chok, Tae Jong Lee, Xiaomei Bu, Meng Luo, Chian Yuh Sin, Yee Mei Foong, Luona Goh, Liang Choo Hsia, Huey Ming Chong
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Publication number: 20060286797Abstract: Example embodiments of a structure and method for forming a copper interconnect having a doped region near a top surface. The doped region has implanted alloying elements that block grain boundaries and reduce stress and electro migration. In a first example embodiment, the barrier layer is left over the inter metal dielectric layer during the alloying element implant. The barrier layer is later removed with a planarization process. In a second example embodiment the barrier layer is removed before the alloying element implant and a hard mask blocks the alloying element from being implanted in the inter metal dielectric layer.Type: ApplicationFiled: June 15, 2005Publication date: December 21, 2006Inventors: Fan Zhang, Kho Liep, Alex See, Cheng-Cheh Tou, Xiaomei Bu, Tae Lee, Liang Hsia
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Patent number: 7094669Abstract: A structure and method of a semiconductor device with liner air gaps next to interconnects and dielectric layers. A dielectric layer is formed over a lower dielectric layer and a lower interconnect over a substrate. We form an interconnect opening in the dielectric layer. The opening has sidewalls of the dielectric layer. A sacrificial liner is formed over the sidewalls of the interconnect opening. An upper interconnect is formed that fills the opening. We remove the sacrificial liner/spacers to form (air) liner gaps.Type: GrantFiled: August 3, 2004Date of Patent: August 22, 2006Assignee: Chartered Semiconductor Manufacturing LTDInventors: Xiaomei Bu, Alex See, Tae Jong Lee, Fan Zhang, Yeon Kheng Lim, Liang Choo Hsia
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Publication number: 20060030128Abstract: A structure and method of a semiconductor device with liner air gaps next to interconnects and dielectric layers. A dielectric layer is formed over a lower dielectric layer and a lower interconnect over a substrate. We form an interconnect opening in the dielectric layer. The opening has sidewalls of the dielectric layer. A sacrificial liner is formed over the sidewalls of the interconnect opening. An upper interconnect is formed that fills the opening. We remove the sacrificial liner/spacers to form (air) liner gaps.Type: ApplicationFiled: August 3, 2004Publication date: February 9, 2006Inventors: Xiaomei Bu, Alex See, Tae Lee, Fan Zhang, Yeon Lim, Liang Hsia
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Publication number: 20050167824Abstract: A method of manufacturing an integrated circuit provides a substrate having a semiconductor device, and includes forming an intermetal dielectric layer over the substrate and the semiconductor device. A metal wire is formed above the semiconductor device and in contact therewith and a passivation layer is formed over the intermetal dielectric layer. A bond pad is formed connected to the metal wire. A protective moat, with sidewall passivation layer, is formed through the passivation layer and the intermetal dielectric layer, and is located between the metal wire and an outside edge of the integrated circuit.Type: ApplicationFiled: January 30, 2004Publication date: August 4, 2005Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Fan Zhang, Kho Chok, Tae Lee, Xiaomei Bu, Meng Luo, Chian Sin, Yee Foong, Luona Goh, Liang Hsia, Huey Chong
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Patent number: 6913994Abstract: An improved method of forming a dual damascene structure that includes an organosilicate glass (OSG) dielectric layer is described. A via first process is followed in which a via is formed in the OSG layer and preferably stops on a SiC layer. The SiC layer is removed prior to stripping a photoresist containing the via pattern. A planarizing BARC layer is formed in the via to protect the exposed substrate from damage during trench formation. The method provides higher Kelvin via and via chain yields. Damage to the OSG layer at top corners of the via and trench is avoided. Furthermore, there is no pitting in the OSG layer at the trench bottom. Vertical sidewalls are achieved in the via and trench openings and via CD is maintained. The OSG loss during etching is minimized by removing the etch stop layer at an early stage of the dual damascene sequence.Type: GrantFiled: April 9, 2003Date of Patent: July 5, 2005Assignee: Agency for Science, Technology and ResearchInventors: Qiang Guo, Ahila Krishnamoorthy, Xiaomei Bu, Vladimir N. Bliznetsov
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Publication number: 20040203223Abstract: An improved method of forming a dual damascene structure that includes an organosilicate glass (OSG) dielectric layer is described. A via first process is followed in which a via is formed in the OSG layer and preferably stops on a SiC layer. The SiC layer is removed prior to stripping a photoresist containing the via pattern. A planarizing BARC layer is formed in the via to protect the exposed substrate from damage during trench formation. The method provides higher Kelvin via and via chain yields. Damage to the OSG layer at top comers of the via and trench is avoided. Furthermore, there is no pitting in the OSG layer at the trench bottom. Vertical sidewalls are achieved in the via and trench openings and via CD is maintained. The OSG loss during etching is minimized by removing the etch stop layer at an early stage of the dual damascene sequence.Type: ApplicationFiled: April 9, 2003Publication date: October 14, 2004Applicant: Institute of MicroelectronicsInventors: Qiang Guo, Ahila Krishnamoorthy, Xiaomei Bu, Vladimir N. Bliznetsov