Patents by Inventor Xiaomin Si
Xiaomin Si has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Digital signal receiver and method for controlling signal processing in such digital signal receiver
Patent number: 10448337Abstract: A digital signal receiver comprises an iterative decoder configured to decode its input signal using an iterative decoding algorithm, a signal quality detector, configured to detect signal quality of the input signal of the iterative decoder; a power consumption monitor, configured to detect a parameter indicating power consumption of the iterative decoder; a voltage regulator, configured to adjust a supply voltage of the iterative decoder to maintain it within a preset supply voltage range, based on the detected parameter indicating the power consumption of the iterative decoder; and an iteration controller, configured to adjust a maximum iteration number of decoding based on the signal quality of the input signal of the iterative decoder.Type: GrantFiled: March 23, 2017Date of Patent: October 15, 2019Assignees: MONTAGE LZ SEMICONDUCTOR (SHANGHAI) CO., LTD., MONTAGE LZ TECHNOLOGIES (CHENGDU) CO., LTD.Inventors: Xiaomin Si, Yu Chen, Yuanfei Nie, Zhen Lu, Qinghai Ren, Ruifeng Lu -
DIGITAL SIGNAL RECEIVER AND METHOD FOR CONTROLLING SIGNAL PROCESSING IN SUCH DIGITAL SIGNAL RECEIVER
Publication number: 20170280396Abstract: A digital signal receiver comprises an iterative decoder configured to decode its input signal using an iterative decoding algorithm, a signal quality detector, configured to detect signal quality of the input signal of the iterative decoder; a power consumption monitor, configured to detect a parameter indicating power consumption of the iterative decoder; a voltage regulator, configured to adjust a supply voltage of the iterative decoder to maintain it within a preset supply voltage range, based on the detected parameter indicating the power consumption of the iterative decoder; and an iteration controller, configured to adjust a maximum iteration number of decoding based on the signal quality of the input signal of the iterative decoder.Type: ApplicationFiled: March 23, 2017Publication date: September 28, 2017Inventors: Xiaomin SI, Yu CHEN, Yuanfei NIE, Zhen LU, Qinghai REN, Ruifeng LU -
Patent number: 9219495Abstract: The application disclose a sigma-delta analog-to-digital converter.Type: GrantFiled: March 17, 2015Date of Patent: December 22, 2015Assignee: MONTAGE TECHNOLOGY (SHANGHAI) CO., LTD.Inventor: Xiaomin Si
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Publication number: 20150280734Abstract: The application disclose a sigma-delta analog-to-digital converter.Type: ApplicationFiled: March 17, 2015Publication date: October 1, 2015Inventor: Xiaomin Si
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Patent number: 8340167Abstract: A method and apparatus for measuring parameters of a receiver having a mixer for generating an I signal and a Q signal using an input signal, an I channel circuit for processing the I signal, and a Q channel circuit for processing the Q signal. The method includes feeding the receiver a first testing signal before the mixer. The method includes feeding the receiver a second testing signal on the I channel circuit. The method includes feeding the receiver a third testing signal on the Q channel circuit. The method includes measuring I/Q quadrature deviation and I/Q delay imbalance of the receiver using the first, the second, and the third testing signals. This separates the I/Q quadrature deviation and I/Q delay imbalance.Type: GrantFiled: August 20, 2009Date of Patent: December 25, 2012Assignee: Montage Technology (Shanghai) Co., Ltd.Inventors: Shen Feng, Gang Hu, Yuanfei Nie, Meiwu Wu, Yu Chen, Xiaomin Si, Yiu Leechung
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Publication number: 20110026570Abstract: A method and apparatus for measuring parameters of a receiver having a mixer for generating an I signal and a Q signal using an input signal, an I channel circuit for processing the I signal, and a Q channel circuit for processing the Q signal. The method includes feeding the receiver a first testing signal before the mixer. The method includes feeding the receiver a second testing signal on the I channel circuit. The method includes feeding the receiver a third testing signal on the Q channel circuit. The method includes measuring I/Q quadrature deviation and I/Q delay imbalance of the receiver using the first, the second, and the third testing signals. This separates the I/Q quadrature deviation and I/Q delay imbalance.Type: ApplicationFiled: August 20, 2009Publication date: February 3, 2011Inventors: Shen Feng, Gang Hu, Yuanfei Nie, Meiwu Wu, Yu Chen, Xiaomin Si, Yiu Leechung
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Patent number: 7764082Abstract: Methods and apparatuses to terminate transmission lines using voltage limiters. In one aspect, a termination circuit is integrated on a substrate to terminate a transmission line connected from outside the substrate. The termination circuit includes: a port to interface with the transmission line; a first resistive path including a first voltage limiter coupled between the port and a first power supply voltage provided on the substrate resistive path; and a second resistive path including a second voltage limiter coupled between the port and a second power supply voltage provided on the substrate.Type: GrantFiled: November 20, 2007Date of Patent: July 27, 2010Inventors: Gang Yan, Xiaomin Si, Larry Wu, Jie Zhang
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Patent number: 7672417Abstract: A data and clock recovery circuit having a retimer mode and a resync mode. In one embodiment, a receiver circuit includes; a retimer; a clock recovery circuit to provide a clock signal to the retimer; and an adjustable delay to provide a delayed version of an input signal to the retimer. When in a resync mode, the adjustable delay causes a pre-selected delay in the input signal and the clock recovery circuit dynamically selects a clock phase to generate the clock signal. When in a second mode, the adjustable delay dynamically adjusts the delayed version of the input signal and the clock recovery circuit outputs the clock signal having a pre-selected clock phase.Type: GrantFiled: August 31, 2006Date of Patent: March 2, 2010Assignee: Montage Technology Group LimitedInventors: Xiaomin Si, Larry Wu
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Publication number: 20090174507Abstract: Methods and apparatuses to terminate transmission lines using voltage limiters. In one aspect, a termination circuit is integrated on a substrate to terminate a transmission line connected from outside the substrate. The termination circuit includes: a port to interface with the transmission line; a first resistive path including a first voltage limiter coupled between the port and a first power supply voltage provided on the substrate resistive path; and a second resistive path including a second voltage limiter coupled between the port and a second power supply voltage provided on the substrate.Type: ApplicationFiled: November 20, 2007Publication date: July 9, 2009Applicant: MONTAGE TECHNOLOGY GROUP, LTD.Inventors: Gang Yan, Xiaomin Si, Lei Wu, Jie Zhang
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Patent number: 7558980Abstract: Systems and methods to distribute clock signals using a common bus. In one embodiment, a clock signal distribution system includes: a bus; a transmitter coupled to the bus to drive a clock signal onto the bus; and one or more receivers coupled to the bus to receive the clock signal, in which the impedance of each receiver is lower than 1000 ohms (or 500 or 200 ohms). In one embodiment, the clock distribution system is on an integrated circuit to distribute the clock on the integrated circuit chip. In one embodiment, the receivers are self-biased; a bias current of the transmitter is a dynamic sum of bias currents of the receivers; and, each of the receivers has a duty cycle correction mechanism. In one embodiment, there is no inductor between the transmitter and the low impedance receiver in the clock distribution system; and the bus has no terminator.Type: GrantFiled: January 4, 2007Date of Patent: July 7, 2009Assignee: Montage Technology Group LimitedInventors: Swee Ann Teo, Xiaomin Si, Larry Wu
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Publication number: 20080165884Abstract: Systems and methods to distribute clock signals using a common bus. In one embodiment, a clock signal distribution system includes: a bus; a transmitter coupled to the bus to drive a clock signal onto the bus; and one or more receivers coupled to the bus to receive the clock signal, in which the impedance of each receiver is lower than 1000 ohms (or 500 or 200 ohms). In one embodiment, the clock distribution system is on an integrated circuit to distribute the clock on the integrated circuit chip. In one embodiment, the receivers are self-biased; a bias current of the transmitter is a dynamic sum of bias currents of the receivers; and, each of the receivers has a duty cycle correction mechanism. In one embodiment, there is no inductor between the transmitter and the low impedance receiver in the clock distribution system; and the bus has no terminator.Type: ApplicationFiled: January 4, 2007Publication date: July 10, 2008Applicant: MONTAGE TECHNOLOGY GROUP, LTDInventors: Swee Ann Teo, Xiaomin Si, Larry Wu
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Patent number: 7366926Abstract: Integrated circuit chips with on-chip supply regulators with programmability and initialization. In one embodiment, an integrated circuit, includes: an initialization circuit to assert an initialization signal during powering up of the integrated circuit; a control circuit coupled to the initialization circuit; and a power supply regulator coupled to the control circuit, the power supply regulator to provide a first voltage to the control circuit when the initialization signal is asserted, the power supply regulator to provide a second voltage to the control circuit according to a control signal from the control circuit when the initialization signal is not asserted. In one embodiment, the integrated circuit includes a digital television demodulator.Type: GrantFiled: June 13, 2006Date of Patent: April 29, 2008Assignee: Montage Technology Group LimitedInventors: Xiaomin Si, Howard Yang, Stephen Tai
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Publication number: 20080056426Abstract: A data and clock recovery circuit having a retimer mode and a resync mode. In one embodiment, a receiver circuit includes: a retimer; a clock recovery circuit to provide a clock signal to the retimer; and an adjustable delay to provide a delayed version of an input signal to the retimer. When in a resync mode, the adjustable delay causes a pre-selected delay in the input signal and the clock recovery circuit dynamically selects a clock phase to generate the clock signal. When in a second mode, the adjustable delay dynamically adjusts the delayed version of the input signal and the clock recovery circuit outputs the clock signal having a pre-selected clock phase.Type: ApplicationFiled: August 31, 2006Publication date: March 6, 2008Applicant: MONTAGE TECHNOLOGY GROUP,LTDInventors: Xiaomin Si, Larry Wu
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Publication number: 20080022324Abstract: In one embodiment, a personal television broadcasting system includes one or more television receivers; and a television signal transmitter coupled to one of: a personal computer, a set top box, a game console, and a portable video player to broadcast video content to the one or more television receivers that are limited within a range of a personal area. In one embodiment, a television signal transmitter is integrated with one of: a personal computer, a set top box, a game console, and a portable video player.Type: ApplicationFiled: July 19, 2006Publication date: January 24, 2008Applicant: MONTAGE TECHNOLOGY GROUP, LTDInventors: Howard Yang, Stephen Tai, Xiaopeng Chen, Xiaomin Si, Larry Wu, Gang Shan, Swee-Ann Teo, Eric Tsang
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Publication number: 20070285122Abstract: Integrated circuit chips with on-chip supply regulators with programmability and initialization. In one embodiment, an integrated circuit, includes: an initialization circuit to assert an initialization signal during powering up of the integrated circuit; a control circuit coupled to the initialization circuit; and a power supply regulator coupled to the control circuit, the power supply regulator to provide a first voltage to the control circuit when the initialization signal is asserted, the power supply regulator to provide a second voltage to the control circuit according to a control signal from the control circuit when the initialization signal is not asserted. In one embodiment, the integrated circuit includes a digital television demodulator.Type: ApplicationFiled: June 13, 2006Publication date: December 13, 2007Applicant: MONTAGE TECHNOLOGY GROUP, LTDInventors: Xiaomin Si, Howard Yang, Stephen Tai
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Patent number: 6236257Abstract: An emitter follower circuit with feed forward compensation includes an emitter follower having an emitter follower input and an emitter follower output. An auxiliary emitter follower has an auxiliary emitter follower input and an auxiliary emitter follower output. The emitter follower input is coupled to the auxiliary emitter follower input and the emitter follower output is capacitively coupled to the auxiliary emitter follower output. In this manner, ringing of the emitter follower circuit with feed forward compensation is reduced by the capacitive coupling of the auxiliary emitter follower output to the emitter follower output.Type: GrantFiled: October 1, 1998Date of Patent: May 22, 2001Assignee: LSI Logic CorporationInventors: Xiaomin Si, Jenn-Gang Chern
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Patent number: 6169458Abstract: A system and method for a differential charge pump with reduced charge-coupling effects for use in integrated circuits such as a phase-lock loop are disclosed. The charge pump includes a first branch, a second branch, and a charge device. The first branch includes a first current source and sink coupled to a power supply and ground, respectively, a first current steering device coupled between the first current source and sink, and a first buffer coupled to the first current steering device between a first charge node and a first damp node. The second branch includes a second current source and sink coupled to a power supply and ground, respectively, a second current steering device coupled between the second current source and sink, and a second buffer coupled to the second current steering device between a second charge node and a second damp node.Type: GrantFiled: September 1, 1999Date of Patent: January 2, 2001Assignee: LSI Logic CorporationInventors: Ravindra U. Shenoy, Xiaomin Si