Abstract: The present disclosure belongs to the field of computational biology and protein engineering technology. The present disclosure provides a protein engineering and directed evolution method based on graph deep learning and applications thereof, the method includes the following steps: S1, construction of a protein structural dataset; S2, protein graph representation; S3, graph neural network model architecture; S4, model training and performance evaluation; S5, model inference, and finally identification of potential mutations that can improve the fitness. The present disclosure can realize zero-shot, low-cost, high-efficiency, and accurate prediction of protein variants with improved properties; meanwhile, TadA8ePro with improved A-to-G base editing efficiency, Cas9Plus with higher gene knockout efficiency, and OsPHR2 transcription factor with improved binding activity are also provided.

Abstract: An encryption/decryption method and a device. The method includes: performing rounds of operations based on input data and a key to generate output data, each round of operations processes N blocks of data to generate round output data; in each round of operations, the method further includes: performing random masking based on the N?1 blocks of data and a round key rki of the i-th round to generate first data; performing nonlinear transformation on the first data using a masked S-box to generate second data; performing linear transformation on the second data to generate third data; performing a first XOR operation on a remaining one block of data of the current round and the third data to generate fourth data; performing masking on the fourth data to generate the round output data of the current round.

Abstract: A signal generator includes a signal output stage circuit, a sensor circuit, and a negative voltage generator circuit. The signal output stage circuit receives an operating voltage and a negative voltage as power supply voltages, and generates an output voltage to drive a load. The sensor circuit detects the load impedance and the operating voltage. The negative voltage generator circuit adjusts the driving capability of the negative voltage based on information related to the operating voltage and information related to the load impedance. The signal output stage circuit adjusts the driving capability of the output voltage based on information related to the load impedance.

Abstract: Disclosed is a phase-locked loop device. The phase-locked loop device includes a frequency-locked loop circuit and a phase-locked loop circuit. The frequency-locked loop circuit includes a delay generator circuit and a frequency-phase detector. The delay generator circuit generates a ramp signal based on the feedback clock signal, and compares the ramp signal with multiple reference voltages to generate multiple delayed feedback clock signals. The frequency-phase detector has a dead zone control mechanism that generates a locking signal based on phases of the reference clock signal and delayed feedback clock signal and automatically switches on/off the dead zone. The phase-locked loop circuit generates the first output current according to the phase difference between the reference clock signal and the feedback clock signal.

Abstract: Disclosed is a phase-locked loop device. The phase-locked loop device includes a frequency-locked loop circuit and a phase-locked loop circuit. The frequency-locked loop circuit includes a delay generator circuit and a frequency-phase detector. The delay generator circuit generates a ramp signal based on the feedback clock signal, and compares the ramp signal with multiple reference voltages to generate multiple delayed feedback clock signals. The frequency-phase detector has a dead zone control mechanism that generates a locking signal based on phases of the reference clock signal and delayed feedback clock signal and automatically switches on/off the dead zone. The phase-locked loop circuit generates the first output current according to the phase difference between the reference clock signal and the feedback clock signal.

Abstract: A digital signal receiver comprises an iterative decoder configured to decode its input signal using an iterative decoding algorithm, a signal quality detector, configured to detect signal quality of the input signal of the iterative decoder; a power consumption monitor, configured to detect a parameter indicating power consumption of the iterative decoder; a voltage regulator, configured to adjust a supply voltage of the iterative decoder to maintain it within a preset supply voltage range, based on the detected parameter indicating the power consumption of the iterative decoder; and an iteration controller, configured to adjust a maximum iteration number of decoding based on the signal quality of the input signal of the iterative decoder.

Abstract: A digital signal receiver comprises an iterative decoder configured to decode its input signal using an iterative decoding algorithm, a signal quality detector, configured to detect signal quality of the input signal of the iterative decoder; a power consumption monitor, configured to detect a parameter indicating power consumption of the iterative decoder; a voltage regulator, configured to adjust a supply voltage of the iterative decoder to maintain it within a preset supply voltage range, based on the detected parameter indicating the power consumption of the iterative decoder; and an iteration controller, configured to adjust a maximum iteration number of decoding based on the signal quality of the input signal of the iterative decoder.

Abstract: The application disclose a sigma-delta analog-to-digital converter.

Abstract: The application disclose a sigma-delta analog-to-digital converter.

Abstract: A method and apparatus for measuring parameters of a receiver having a mixer for generating an I signal and a Q signal using an input signal, an I channel circuit for processing the I signal, and a Q channel circuit for processing the Q signal. The method includes feeding the receiver a first testing signal before the mixer. The method includes feeding the receiver a second testing signal on the I channel circuit. The method includes feeding the receiver a third testing signal on the Q channel circuit. The method includes measuring I/Q quadrature deviation and I/Q delay imbalance of the receiver using the first, the second, and the third testing signals. This separates the I/Q quadrature deviation and I/Q delay imbalance.

Abstract: A method and apparatus for measuring parameters of a receiver having a mixer for generating an I signal and a Q signal using an input signal, an I channel circuit for processing the I signal, and a Q channel circuit for processing the Q signal. The method includes feeding the receiver a first testing signal before the mixer. The method includes feeding the receiver a second testing signal on the I channel circuit. The method includes feeding the receiver a third testing signal on the Q channel circuit. The method includes measuring I/Q quadrature deviation and I/Q delay imbalance of the receiver using the first, the second, and the third testing signals. This separates the I/Q quadrature deviation and I/Q delay imbalance.

Abstract: Methods and apparatuses to terminate transmission lines using voltage limiters. In one aspect, a termination circuit is integrated on a substrate to terminate a transmission line connected from outside the substrate. The termination circuit includes: a port to interface with the transmission line; a first resistive path including a first voltage limiter coupled between the port and a first power supply voltage provided on the substrate resistive path; and a second resistive path including a second voltage limiter coupled between the port and a second power supply voltage provided on the substrate.

Abstract: A data and clock recovery circuit having a retimer mode and a resync mode. In one embodiment, a receiver circuit includes; a retimer; a clock recovery circuit to provide a clock signal to the retimer; and an adjustable delay to provide a delayed version of an input signal to the retimer. When in a resync mode, the adjustable delay causes a pre-selected delay in the input signal and the clock recovery circuit dynamically selects a clock phase to generate the clock signal. When in a second mode, the adjustable delay dynamically adjusts the delayed version of the input signal and the clock recovery circuit outputs the clock signal having a pre-selected clock phase.

Abstract: Methods and apparatuses to terminate transmission lines using voltage limiters. In one aspect, a termination circuit is integrated on a substrate to terminate a transmission line connected from outside the substrate. The termination circuit includes: a port to interface with the transmission line; a first resistive path including a first voltage limiter coupled between the port and a first power supply voltage provided on the substrate resistive path; and a second resistive path including a second voltage limiter coupled between the port and a second power supply voltage provided on the substrate.

Abstract: Systems and methods to distribute clock signals using a common bus. In one embodiment, a clock signal distribution system includes: a bus; a transmitter coupled to the bus to drive a clock signal onto the bus; and one or more receivers coupled to the bus to receive the clock signal, in which the impedance of each receiver is lower than 1000 ohms (or 500 or 200 ohms). In one embodiment, the clock distribution system is on an integrated circuit to distribute the clock on the integrated circuit chip. In one embodiment, the receivers are self-biased; a bias current of the transmitter is a dynamic sum of bias currents of the receivers; and, each of the receivers has a duty cycle correction mechanism. In one embodiment, there is no inductor between the transmitter and the low impedance receiver in the clock distribution system; and the bus has no terminator.

Abstract: Systems and methods to distribute clock signals using a common bus. In one embodiment, a clock signal distribution system includes: a bus; a transmitter coupled to the bus to drive a clock signal onto the bus; and one or more receivers coupled to the bus to receive the clock signal, in which the impedance of each receiver is lower than 1000 ohms (or 500 or 200 ohms). In one embodiment, the clock distribution system is on an integrated circuit to distribute the clock on the integrated circuit chip. In one embodiment, the receivers are self-biased; a bias current of the transmitter is a dynamic sum of bias currents of the receivers; and, each of the receivers has a duty cycle correction mechanism. In one embodiment, there is no inductor between the transmitter and the low impedance receiver in the clock distribution system; and the bus has no terminator.

Abstract: Integrated circuit chips with on-chip supply regulators with programmability and initialization. In one embodiment, an integrated circuit, includes: an initialization circuit to assert an initialization signal during powering up of the integrated circuit; a control circuit coupled to the initialization circuit; and a power supply regulator coupled to the control circuit, the power supply regulator to provide a first voltage to the control circuit when the initialization signal is asserted, the power supply regulator to provide a second voltage to the control circuit according to a control signal from the control circuit when the initialization signal is not asserted. In one embodiment, the integrated circuit includes a digital television demodulator.

Abstract: A data and clock recovery circuit having a retimer mode and a resync mode. In one embodiment, a receiver circuit includes: a retimer; a clock recovery circuit to provide a clock signal to the retimer; and an adjustable delay to provide a delayed version of an input signal to the retimer. When in a resync mode, the adjustable delay causes a pre-selected delay in the input signal and the clock recovery circuit dynamically selects a clock phase to generate the clock signal. When in a second mode, the adjustable delay dynamically adjusts the delayed version of the input signal and the clock recovery circuit outputs the clock signal having a pre-selected clock phase.

Abstract: In one embodiment, a personal television broadcasting system includes one or more television receivers; and a television signal transmitter coupled to one of: a personal computer, a set top box, a game console, and a portable video player to broadcast video content to the one or more television receivers that are limited within a range of a personal area. In one embodiment, a television signal transmitter is integrated with one of: a personal computer, a set top box, a game console, and a portable video player.

Abstract: Integrated circuit chips with on-chip supply regulators with programmability and initialization. In one embodiment, an integrated circuit, includes: an initialization circuit to assert an initialization signal during powering up of the integrated circuit; a control circuit coupled to the initialization circuit; and a power supply regulator coupled to the control circuit, the power supply regulator to provide a first voltage to the control circuit when the initialization signal is asserted, the power supply regulator to provide a second voltage to the control circuit according to a control signal from the control circuit when the initialization signal is not asserted. In one embodiment, the integrated circuit includes a digital television demodulator.