Abstract: The present disclosure relates to methods, devices, systems, and techniques for forming semiconductor devices. An example semiconductor device includes a first stack of conductive layers and isolating layers alternating with each other along a first direction and a second stack of dielectric layers and isolating layers alternating with each other along the first direction. The semiconductor device further includes an isolating wall between the first stack and the second stack along a second direction perpendicular to the first direction. The isolating wall includes isolating structures extending along the first direction and being aligned along a third direction perpendicular to the first direction and the second direction. The semiconductor device further includes contact structures extending through at least a part of the second stack along the first direction and connecting structures extending through the isolating wall along the second direction.

Abstract: Memory device, memory system and formation method are provided. The method includes forming a sacrificial layer over a dielectric-pair stack, the sacrificial layer containing a top selective gate (TSG) cut structure over the dielectric-pair stack; forming a channel plug structure including a lower plug portion in the dielectric-pair stack and an upper plug portion through the sacrificial layer; forming a barrier layer at least enveloping the upper plug portion of the channel plug structure after a removal of the sacrificial layer; and forming a semiconductor layer over the dielectric-pair stack to embed the TSG cut structure, the barrier layer, and the upper plug portion of the channel plug structure.

Abstract: The present disclosure relates to methods, devices, and systems for managing isolating structures in semiconductor devices. An example semiconductor device includes a first stack of conductive layers and isolating layers extending along a first direction and alternating with each other along a second direction perpendicular to the first direction. The semiconductor device further includes a gate line slit structure extending through the first stack along the second direction, and a first isolating structure extending along the first direction. The first isolating structure includes a first portion in the first stack and a second portion in the gate line slit structure. A size of the first portion is greater than a size of the second portion along the second direction.

Abstract: Memory device, memory system and formation method are provided. The method includes forming a sacrificial layer over a dielectric-pair stack, the sacrificial layer containing a top selective gate (TSG) cut structure over the dielectric-pair stack; forming a channel plug structure including a lower plug portion in the dielectric-pair stack and an upper plug portion through the sacrificial layer; forming a barrier layer at least enveloping the upper plug portion of the channel plug structure after a removal of the sacrificial layer; and forming a semiconductor layer over the dielectric-pair stack to embed the TSG cut structure, the barrier layer, and the upper plug portion of the channel plug structure.

Abstract: A memory device includes a stack structure including a plurality of gate lines and a select gate line, a first channel structure extending through the plurality of gate lines along a first direction, a dielectric layer disposed on the first channel structure and the select gate line, and extending along a second direction perpendicular to the first direction, and a conductive layer disposed in the dielectric layer, and the conductive layer in contact with the select gate line.

Abstract: A semiconductor device includes a first stack of alternating first word line layers and first insulating layers over a semiconductor layer. A first channel structure extends from the semiconductor layer and through a first array region of the first stack. A second stack of alternating second word line layers and second insulating layers are over the first stack. A second channel structure extends from the first channel structure and through a second array region of the second stack. A thickness of a particular first insulating layer, which is positioned closest to the second stack relative to other first insulating layers, is a sum of at least two times an average thickness of the other first insulating layers and at least one time an average thickness of the first word line layers in the first array region.

Abstract: Systems, devices, and methods for managing three-dimensional (3D) semiconductor devices are provided. In one aspect, a semiconductor device includes a stack structure with at least one gate line, a select gate layer and at least one channel structure. The at least one gate line includes a first material. The select gate layer includes a second material different from the first material. The at least one channel structure extends through the stack structure and the select gate layer along a first axis. Each channel structure of the at least one channel structure includes a layered structure.

Abstract: A support structure for a plurality of solar cells includes a truss and a plate engaged with the truss. The plate includes a plurality of polygonal panels. The plurality of polygonal panels are arranged such that the plate has a non-planar surface. Each polygonal panel of the plurality of polygonal panels is configured to support at least one solar cell of the plurality of solar cells.

Abstract: The present disclosure provides a pre-reduced pellet preparation device and method based on grate-rotary kiln. The pre-reduced pellet preparation device comprises a grate-rotary kiln pellet oxidation system and a hydrogen-based shaft furnace reduction system.

Abstract: Memory device, memory system and formation method are provided. The method includes forming a sacrificial layer over a dielectric-pair stack, the sacrificial layer containing a top selective gate (TSG) cut structure over the dielectric-pair stack; forming a channel plug structure including a lower plug portion in the dielectric-pair stack and an upper plug portion through the sacrificial layer; forming a barrier layer at least enveloping the upper plug portion of the channel plug structure after a removal of the sacrificial layer; and forming a semiconductor layer over the dielectric-pair stack to embed the TSG cut structure, the barrier layer, and the upper plug portion of the channel plug structure.

Abstract: Semiconductor components, fabrication methods thereof and memory systems. A fabrication method includes performing trap repairing on a first wafer at a first temperature, the first wafer including memory cells; bonding the first wafer with a second wafer to form a semiconductor component, the second wafer including a device layer; and repairing the semiconductor component at a second temperature lower than the first temperature.

Abstract: A semiconductor device includes a stack structure and channel holes penetrating through the stack structure. The stack structure includes alternately stacked dielectric layers and conductive layers, the conductive layers including a top select gate layer. The top select gate layer is provided with a first top select gate isolation structure and a second top select gate isolation structure, and the channel holes are located between the first top select gate isolation structure and the second top select gate isolation structure. The second top select gate isolation structure includes an insulation portion, and the insulation portion is divided into a plurality of second top select gate isolation substructures, so that the critical dimension (CD) of the second top select gate isolation substructure may be matched with the CD of the first top select gate isolation structure.

Abstract: A semiconductor device includes a first stack of alternating first word line layers and first insulating layers over a semiconductor layer. A first channel structure extends from the semiconductor layer and through a first array region of the first stack. A second stack of alternating second word line layers and second insulating layers are over the first stack. A second channel structure extends from the first channel structure and through a second array region of the second stack. A thickness of a particular first insulating layer, which is positioned closest to the second stack relative to other first insulating layers, is a sum of at least two times an average thickness of the other first insulating layers and at least one time an average thickness of the first word line layers in the first array region.

Abstract: A semiconductor device includes a first stack of alternating first word line layers and first insulating layers over a semiconductor layer. The first stack includes a first array region and a first staircase region adjacent to the first array region. The semiconductor device includes a second stack of alternating second word line layers and second insulating layers, where the second stack includes a second array region over the first array region and a second staircase region adjacent to the second array region and over the first staircase region. The first stack further includes a first transition layer over the first word line layers. The first transition layer includes a first dielectric portion in the first array region that surrounds the first channel structure and a first conductive portion. The first transition layer is disposed between two adjacent first insulating layers of the first insulating layers.