Abstract: A merge sort circuit can include a parallel merge sort core that performs a partial merge on two input tuples, each containing a number P of data elements sorted according to a sort key, to produce a sorted output tuple of P data elements. Input data blocks to be merged can be stored in first and second block buffers. The block buffers can receive data from a vector memory read interface that reads groups of at least P data elements at a time. Loading of data elements into the block buffers can be based on respective fill levels of the block buffers.

Abstract: A merge sort circuit can include a parallel merge sort core that performs a partial merge on two input tuples, each containing a number P of data elements sorted according to a sort key, to produce a sorted output tuple of P data elements. Input data blocks to be merged can be stored in first and second block buffers. The block buffers can receive data from a vector memory read interface that reads groups of at least P data elements at a time. Loading of data elements into the block buffers can be based on respective fill levels of the block buffers.

Abstract: According to one embodiment, a connection is established between a first communication device and a second communication device in accordance with one or more communication layers. Each communication layer is associated with a standard structure and protocol. An ad hoc communication layer structure and/or protocol are determined at the first communication device. The ad hoc communication layer structure and/or protocol are communicated to the second communication device. One or more of the standard structures and/or protocols are replaced at the first communication device with the ad hoc communication layer structure and/or protocol responsive to the second communication device acknowledging acceptance of the ad hoc communication layer structure and/or protocol.

Abstract: The disclosure relates to a data processing device, comprising: a processing element configured to process a plurality of data packets according to a communication protocol to provide a plurality of processed data packets each comprising a first part and a second part; and an interface configured to offload the second parts of the plurality of processed data packets to a remote data processing device and configured to notify the remote processing device of the offload of the second parts of the plurality of processed data packets.

Abstract: According to one embodiment, a connection is established between a first communication device and a second communication device in accordance with one or more communication layers. Each communication layer is associated with a standard structure and protocol. An ad hoc communication layer structure and/or protocol are determined at the first communication device. The ad hoc communication layer structure and/or protocol are communicated to the second communication device. One or more of the standard structures and/or protocols are replaced at the first communication device with the ad hoc communication layer structure and/or protocol responsive to the second communication device acknowledging acceptance of the ad hoc communication layer structure and/or protocol.

Abstract: According to one embodiment, a connection is established between a first communication device and a second communication device in accordance with one or more communication layers. Each communication layer is associated with a standard structure and protocol. An ad hoc communication layer structure and/or protocol are determined at the first communication device. The ad hoc communication layer structure and/or protocol are communicated to the second communication device. One or more of the standard structures and/or protocols are replaced at the first communication device with the ad hoc communication layer structure and/or protocol responsive to the second communication device acknowledging acceptance of the ad hoc communication layer structure and/or protocol.

Abstract: The disclosure relates to a data processing device, comprising: a processing element configured to process a plurality of data packets according to a communication protocol to provide a plurality of processed data packets each comprising a first part and a second part; and an interface configured to offload the second parts of the plurality of processed data packets to a remote data processing device and configured to notify the remote processing device of the offload of the second parts of the plurality of processed data packets.

Abstract: The disclosure relates to a data processing device, comprising: a processing element configured to process a plurality of data packets according to a communication protocol to provide a plurality of processed data packets each comprising a first part and a second part; and an interface configured to offload the second parts of the plurality of processed data packets to a remote data processing device and configured to notify the remote processing device of the offload of the second parts of the plurality of processed data packets.

Abstract: The disclosure relates to a data processing device, comprising: a processing element configured to process a plurality of data packets according to a communication protocol to provide a plurality of processed data packets each comprising a first part and a second part; and an interface configured to offload the second parts of the plurality of processed data packets to a remote data processing device and configured to notify the remote processing device of the offload of the second parts of the plurality of processed data packets.

Abstract: According to one embodiment, a connection is established between a first communication device and a second communication device in accordance with one or more communication layers. Each communication layer is associated with a standard structure and protocol. An ad hoc communication layer structure and/or protocol are determined at the first communication device. The ad hoc communication layer structure and/or protocol are communicated to the second communication device. One or more of the standard structures and/or protocols are replaced at the first communication device with the ad hoc communication layer structure and/or protocol responsive to the second communication device acknowledging acceptance of the ad hoc communication layer structure and/or protocol.

Abstract: According to one embodiment, a connection is established between a first communication device and a second communication device in accordance with one or more communication layers. Each communication layer is associated with a standard structure and protocol. An ad hoc communication layer structure and/or protocol are determined at the first communication device. The ad hoc communication layer structure and/or protocol are communicated to the second communication device. One or more of the standard structures and/or protocols are replaced at the first communication device with the ad hoc communication layer structure and/or protocol responsive to the second communication device acknowledging acceptance of the ad hoc communication layer structure and/or protocol.

Abstract: A data moving processor includes a code memory coupled to a code fetch circuit and a decode circuit coupled to the code fetch circuit. An address stack is coupled to the decode circuit and configured to store address data. A general purpose stack is coupled to the decode circuit and configured to store other data. The data moving processor uses data from the general purpose stack to perform calculations. The data moving processor uses address data from the address stack to identify source and destination memory locations. The address data may be used to drive an address line of a memory during a read or write operation. The address stack and general purpose stack are separately controlled using bytecode.

Abstract: A computing device includes a hardware data processing unit having at least one input buffer, a plurality of output buffers, a data transfer unit, and a software control unit, the data transfer unit configured to transfer data from the input buffer to the plurality of output buffers, and the software control unit configured to control the data transfer unit.

Abstract: In order to be able to use a smaller routing table (4) and, thus, to reduce the costs and power consumption and to improve the performance of an IP router, it is proposed to extract a destination address identifier (ADR) from a data packet to be forwarded by the IP router, compress the extracted destination address identifier (ADR) by using a lossless data compression algorithm, and compare the compressed destination address identifier with entries stored in the routing table (4) so as to find a correspondence between the destination address identifier and one of the entries of the routing table (4). Each entry of the routing table (4) corresponds to a possible or available forwarding address of the IP router, the forwarding addresses having been compressed with the same data compression algorithm as the destination address identifier.

Abstract: A system and method for processing data is disclosed. In one embodiment, a data moving processor comprises a code memory coupled to a code fetch circuit and a decode circuit coupled to the code fetch circuit. An address stack is coupled to the decode circuit and configured to store address data. A general purpose stack is coupled to the decode circuit and configured to store other data. The data moving processor uses data from the general purpose stack to perform calculations. The data moving processor uses address data from the address stack to identify source and destination memory locations. The address data may be used to drive an address line of a memory during a read or write operation. The address stack and general purpose stack are separately controlled using bytecode.

Abstract: According to one embodiment, a connection is established between a first communication device and a second communication device in accordance with one or more communication layers. Each communication layer is associated with a standard structure and protocol. An ad hoc communication layer structure and/or protocol are determined at the first communication device. The ad hoc communication layer structure and/or protocol are communicated to the second communication device. One or more of the standard structures and/or protocols are replaced at the first communication device with the ad hoc communication layer structure and/or protocol responsive to the second communication device acknowledging acceptance of the ad hoc communication layer structure and/or protocol.

Abstract: According to one embodiment, data is transmitted from a first communication device to a second communication device in accordance with one or more communication layer functions of a communication standard including at least a data link layer function. An executable description of at least a new data link layer function is generated at the first communication device. At least the data link layer function of the communication standard is replaced with the new data link layer function at the first communication device.

Abstract: An arrangement and a method for processing data of multiprotocol data packets comprises at least one multiplexer connected to input ports; at least one first programmable data processing unit configured to provide header words and into payload words; a buffer management unit configured to generate localization data which specifies a corresponding memory area of the payload memory; a descriptor generator unit for generating data packet descriptors; a RISC processor configured to generate, in dependence on the data packet descriptors, header data for transmit data packets and payload processing instructions for processing data of the data packet payload words, stored in the payload memory, of the associated received data packet; and at least one second programmable data processing unit configured to process the payload words from the payload memory in accordance with the payload processing instructions and assembles the payload words with the header data to form transmit data packets.

Abstract: Methods, apparatuses, and software for storing a first portion of a data transfer descriptor in cached address space, and storing a second portion of the data transfer descriptor in uncached address space. Also, methods, apparatuses, and software for reading at least a portion of a data transfer descriptor from cached address space, initiating a memory transfer based on the data transfer descriptor, and storing a parameter indicating a status of the data transfer descriptor in uncached address space.

Abstract: The present invention relates to a parallel multithread processor (1) with split contexts, with M parallel-connected standard processor root units (2) being provided for instruction execution of program instructions for different threads (T), and with N context memories (3) being provided, which each temporarily store a current state of a thread (T), and with a thread monitoring unit (4) being provided, by means of which each standard processor root unit (2) can be connected to each context memory (3). The invention accordingly provides a processor architecture in which a number N of different context memories (3) and corresponding threads (T) are effectively fully networked with a number M of standard processor root units (2). This means that use is made not only of paralleling of the standard processor root units (2), but also of the threads (T) and of the context memories (3).