Abstract: Various embodiments provide a charge model for a cell instance for delay calculation of a circuit design that includes the cell instance, where the charge model can be part of electronic design automation (EDA) and used in timing analysis of a circuit design that includes the cell instance. The charge model generated by an embodiment can predict a charge at an input of a cell instance for an arbitrary input voltage waveform and can address (e.g., reduce or negate) a time delay impact the Miller effect has on the cell instance.

Abstract: An example of an apparatus may comprise a first set of compression contact pads formed on a first side of a circuit board, a second set of compression contact pads formed on a second side of the circuit board opposite to the first side of the circuit board, where the first set of compression contact pads are respectively electrically connected to the second set of compression pads. An example of the circuit board may include a memory board. An example stackable memory module may include memory devices mounted to both sides of the memory board. Other examples are disclosed and claimed.

Abstract: An embodiment of an electronic apparatus comprises a circuit board, one or more memory devices affixed to a top side of the circuit board, and one or more board-to-board connectors affixed to a bottom side of the circuit board to provide an external connection to signals of the one or more memory devices, where the one or more board-to-board connectors are located inward from outermost edges of the circuit board and where a first footprint defined by an outermost boundary of the one or more board-to-board connectors is substantially a same size as or smaller than a second footprint defined by an outermost boundary of the one or more memory devices. Other embodiments are disclosed and claimed.

Abstract: An improved approach for implementing metal fill on an electrical device without causing creating cross-coupling capacitance problems is disclosed. Timing aware metal fill insertion is performed to avoid or minimize cross-capacitance problems on the IC design. A cost may be assigned to different candidate metal fill shapes. The cost is associated with the expected effect upon timing requirements by the metal fill shape, with lower costs corresponding to lower expected impacts upon the timing requirements. To meet density requirements, lower cost metal fill shapes are inserted prior to higher cost metal fill shapes.

Abstract: Embodiments of the present invention describe a device and method of mitigating radio frequency interference (REI) in an electronic device. The electronic device comprises a housing, and a thermal energy storage material is formed in the housing. By increasing the loss tangent parameter of the thermal energy storage material, the REI of the electronic device is reduced.

Abstract: A method is provided to produce a model of an integrated circuit substrate, the method comprising: providing a tile definition that specifies an electrical model associated with instances of the tile; mapping a plurality of respective tile instances to respective locations of the substrate; and connecting the mapped tile instances to each other to produce a tile grid that models overall electrical behavior of the substrate.

Abstract: A method is provided to evaluate substrate noise propagation in an integrated circuit design, the method comprising: providing a tile definition that specifies an electrical model associated with instances of the tile; mapping a plurality of respective tile instances to respective locations of the substrate; obtaining respective waveforms indicative of digital switching induced power grid fluctuations associated with the respective identified contacts; and associating a voltage with a selected tile instance of the tile grid that is indicative of substrate noise injection due to waveforms associated with contacts encompassed by the selected tile instance.

Abstract: A methodology is provided to perform noise analysis in the implementation stage of the design of an integrated circuit, and based upon analysis results, a floorplan may be adjusted or guard rings may be inserted to reduce the impact of digital switching noise upon noise sensitive circuits.

Abstract: The present invention discloses a DC/AC converter in the backlight power supply system using cold cathode fluorescent lamp (CCFL). The DC/AC converter comprises a front end DC/DC converter, a full-bridge or half bridge inverter, and a piezoelectric transformer. Even with a wide range of input voltages, the front end DC/DC converter produces a predetermined DC voltage or a DC voltage with a predetermined small range and the cascaded inverter operates with a switching frequency close to the resonant frequency of the piezoelectric transformer, which helps the backlight power supply system achieve high efficiency.

Abstract: Embodiments of the present invention describe a device and method of mitigating radio frequency interference (REI) in an electronic device. The electronic device comprises a housing, and a thermal energy storage material is formed in the housing. By increasing the loss tangent parameter of the thermal energy storage material, the REI of the electronic device is reduced.

Abstract: Disclosed is an improved method and system for implementing metal fill for an integrated circuit design. When an engineering change order is implemented, the existing dummy metal fill geometries are initially ignored when modifying the layout, even if this results in shorts and/or other DRC violations. Once the ECO changes have been implemented, those violations caused by interaction between the changes and the metal fill are repaired afterwards.

Abstract: An improved method, system, and article of manufacture for reducing via failures is described. In one approach, additional vias or via cuts are inserted into an IC device to increase the number of cuts in a given area. The additional vias or via cuts are inserted until a sufficient via density level has been reached.

Abstract: A step up converter with overcurrent protection is disclosed. The step up converter can precisely limit the output current of the upstream device. Current from the input terminal of the converter is detected and compared with a predetermined maximum current to get a comparison value which is delivered to a close-loop regulator. The overcurrent protection is achieved by the regulator outputting a control signal to fulfill the conduction or resistance increase of a resistive element of the protection circuit. Furthermore, detection of the temperature or the output voltage may trigger shut off of the protection circuit to implement a protection function.

Abstract: In some embodiments, an electronic apparatus comprises a display assembly, a printed circuit board comprising a display driver integrated circuit, and at least one structure to alter a resonance frequency characteristic of at least one of the display assembly or the printed circuit board. Other embodiments may be disclosed.

Abstract: A method is provided to evaluate substrate noise propagation in an integrated circuit design, the method comprising: providing a tile definition that specifies an electrical model associated with instances of the tile; mapping a plurality of respective tile instances to respective locations of the substrate; obtaining respective waveforms indicative of digital switching induced power grid fluctuations associated with the respective identified contacts; and associating a voltage with a selected tile instance of the tile grid that is indicative of substrate noise injection due to waveforms associated with contacts encompassed by the selected tile instance.

Abstract: A method is provided to produce a model of an integrated circuit substrate, the method comprising: providing a tile definition that specifies an electrical model associated with instances of the tile; mapping a plurality of respective tile instances to respective locations of the substrate; and connecting the mapped tile instances to each other to produce a tile grid that models overall electrical behavior of the substrate.

Abstract: The present invention discloses a DC/AC converter in the backlight power supply system using cold cathode fluorescent lamp (CCFL). The DC/AC converter comprises a front end DC/DC converter, a full-bridge or half bridge inverter, and a piezoelectric transformer. Even with a wide range of input voltages, the front end DC/DC converter produces a predetermined DC voltage or a DC voltage with a predetermined small range and the cascaded inverter operates with a switching frequency close to the resonant frequency of the piezoelectric transformer, which helps the backlight power supply system achieve high efficiency.

Abstract: The present invention provides a self-driving circuit of a low voltage, large current, and high power density DC/DC converter. The converter comprises a transformer, power MOS transistors (S), output rectification portion (SRb 1, SR2), filter portion and demagnetizing portion. The first configuration of the self-driving circuit consists of Da, Ra, Ca, Qa for self-driving SR2; and the second configuration consists of Da, Ra, Sa, a delay driving circuit and an isolation differential circuit, for self-driving SR2. The self-driving circuit of the present invention may reduce the cross-conductive loss, and increase the converting efficiency.

Abstract: The present invention provides a self-driving circuit for DC/DC converter of a low voltage, high current, and high power density. The converter comprises a transformer, output rectification portion SR1 and voltage clamping. The first configuration of the self-driving circuit consists of resisters Ra1, Ra2, capacitors Ca1, Ca2, transistors Qa1, Qa2; and the second configuration consists of Da, small power MOS transistor SRa, an auxiliary winding Nsa, a delay driving circuit and a isolating differential circuit. The self-driving circuit of the present invention may reduce the cross-conductive loss, and increase the converting efficiency.