Abstract: A sigma-delta analog-to-digital converter is provided that includes an initial continuous-time integration stage having a variable input resistor and an integration capacitor. A switched-capacitor circuit charges and discharges a replica capacitor to a reference voltage to generate a bias current. A SAR-based tuning circuit includes a variable tuning resistor that generates a tuning voltage while conducting a mirrored version of the bias current. A resistance of the variable input resistor is adjusted responsive to a tuning code from the SAR-based tuning circuit.

Abstract: A duty-cycle-insensitive current source includes a first switched-capacitor resistor and a second switched-capacitor resistor. During a first clock phase of a clock signal, the duty-cycle-insensitive current source charges a first capacitor in first switched-capacitor resistor to a reference voltage. During a second clock phase of the clock signal, the duty-cycle-insensitive current source charges a second capacitor in the first switched-capacitor resistor to the reference voltage.

Abstract: An ADC with built-in charge-based capacitance measurements is described. An example includes a plurality of capacitors coupled in parallel to an input voltage at a common node, a plurality of drivers each coupled to a respective capacitor opposite the common node, a first switch coupled to the common node to couple the common node to a ground in response to a second clock signal from a timing generator, a second switch coupled to the common node to couple the common node to a reference voltage in response to a third clock signal from the timing generator, a successive logic circuit configured to control each driver to alternately drive the second clock signal to a selected capacitor or to couple the selected capacitor to ground, and measurement logic including a current sensor to measure a current through the common node and configured to determine a capacitance of the selected capacitor.

Abstract: Aspects of the present disclosure provide input-adaptive analog-to-digital conversion in which the number of conversion cycles used to convert an input signal into a digital signal is adapted based on the level (i.e., amplitude) of the input voltage. In certain aspects, the input voltage is compared with one or more threshold voltages, and the number of conversion cycles is determined based on the comparison. In certain aspects, a most significant bit (MSB) capacitor in a capacitive digital-to-analog (DAC) is split into two or more capacitors to provide the one or more threshold voltages.

Abstract: Aspects of the present disclosure provide input-adaptive analog-to-digital conversion in which the number of conversion cycles used to convert an input signal into a digital signal is adapted based on the level (i.e., amplitude) of the input voltage. In certain aspects, the input voltage is compared with one or more threshold voltages, and the number of conversion cycles is determined based on the comparison. In certain aspects, a most significant bit (MSB) capacitor in a capacitive digital-to-analog (DAC) is split into two or more capacitors to provide the one or more threshold voltages.

Abstract: An apparatus including: a boost voltage generator configured to generate a boost voltage at an output; a first field effect transistor (FET) including a drain/source terminal coupled to the output of the boost voltage generator; a discharging circuit coupled to a source/drain terminal of the first FET, wherein the discharging circuit is configured to discharge the output of the boost voltage generator via the first FET in response to an asserted discharging signal; and a gate voltage boost circuit configured to generate a gate voltage for a gate of the first FET, wherein the gate voltage boost circuit is configured to boost the gate voltage in response to the asserted discharging signal. Another implementation may include a current injection circuit configured to generate and inject a current into the discharging circuit in lieu of or in addition to the gate voltage boost circuit.

Abstract: In certain aspects, a voltage regulator includes a pass device coupled between an input of the voltage regulator and an output of the voltage regulator. The voltage regulator also includes an amplifying circuit having a first input, a second input, and an output, wherein the first input is configured to receive a reference voltage, the second input is coupled to the output of the voltage regulator via a feedback path, and the output of the amplifying circuit is coupled to a gate of the pass device. The voltage regulator further includes a first current source coupled between a supply rail and the amplifying circuit, and a capacitor coupled between the first current source and the output of the voltage regulator.

Abstract: In certain aspects, a voltage regulator includes a pass device coupled between an input of the voltage regulator and an output of the voltage regulator. The voltage regulator also includes an amplifying circuit having a first input, a second input, and an output, wherein the first input is configured to receive a reference voltage, the second input is coupled to the output of the voltage regulator via a feedback path, and the output of the amplifying circuit is coupled to a gate of the pass device. The voltage regulator further includes a first current source coupled between a supply rail and the amplifying circuit, and a capacitor coupled between the first current source and the output of the voltage regulator.