Abstract: The present disclosure provides a method of voice chip implementation, a voice chip, an intelligent voice product, an electronic device, and a storage medium, and relates to the field of artificial intelligence (AI) such as intelligent voice and AI chips. The method may include: constructing a voice chip including a first Digital Signal Processor (DSP) and a second DSP, the first DSP and the second DSP corresponding to a same Digital Signal Processor core Identifier (DSP core IP) and adopting heterogeneous designs; and completing a chip processing function in a corresponding intelligent voice product by using the voice chip, wherein different functions are completed by using the first DSP and the second DSP respectively. By use of the solutions of the present disclosure, implementation costs can be reduced.

Abstract: A processor, processor implementation method, and a storage medium are disclosed, which relates to the field of artificial intelligence and deep learning. The processor includes: a system controller a data packing and unpacking module, a storage array module, and an operation module configured to perform operation processing on the acquired first packet, generate the second packet according to the operation result data, and return the second packet to the data packing and unpacking module. The storage array module comprises N1 storage units. The data packing and unpacking module comprises N2 data packing and unpacking units, each of the data packing and unpacking units is connected to the routing and switching module through a data channel. The universal operation module comprises M operation units. The activation operation module comprises P operation unit, each of the operation units is connected to the routing and switching module through a data channel.

Abstract: A processor, processor implementation method, and a storage medium are disclosed, which relates to the field of artificial intelligence and deep learning. The processor includes: a system controller a data packing and unpacking module, a storage array module, and an operation module configured to perform operation processing on the acquired first packet, generate the second packet according to the operation result data, and return the second packet to the data packing and unpacking module. The storage array module comprises N1 storage units. The data packing and unpacking module comprises N2 data packing and unpacking units, each of the data packing and unpacking units is connected to the routing and switching module through a data channel. The universal operation module comprises M operation units. The activation operation module comprises P operation unit, each of the operation units is connected to the routing and switching module through a data channel.

Abstract: The present disclosure discloses a speech chip and an electronic device. The speech chip includes a first processing module, a second processing module and a third processing module. The first processing module is configured to run an operating system, and to perform data scheduling on modules other than the first processing module in the chip. The second processing module is configured to perform a mutual conversion between speech and text based on a speech model. The third processing module is configured to perform digital signal processing on inputted speech.

Abstract: A processor includes a system controller configured to send predetermined packet information to a data packing and unpacking module; the data packing and unpacking module configured to acquire corresponding packet data from a storage array module according to the packet information, pack the packet data with the packet information, send a first packet obtained from packing to an operation module for operation processing, acquire a second packet returned by the operation module, unpack the second packet to obtain operation result data, and store the operation result data in the storage array module; the storage array module configured to store data; and the operation module configured to perform operation processing on the acquired first packet, generate the second packet according to the operation result data, and return the second packet to the data packing and unpacking module.

Abstract: A spin coating device and method. The spin coating device includes a rotatable rotary shaft and sucker fixed on an end portion of the shaft, and an electromagnetic induction device below the sucker which includes an annular magnet fixed below the sucker, coil group formed by a first and second coil, and strip-shaped magnet fixed at the rotary shaft. A base on the sucker has a notch. The unbalanced centrifugal force during rotation of the sucker causes vibration. The electromagnetic induction device enables the centrifugal force generated during rotation of the sucker to be in balance with the magnetic force generated by the electromagnetic induction device to adjust the levelness of the sucker surface. The device does not need manual manipulation, enables the sucker to be more stable, reduces damage to the equipment due to vibration, and improves the effect of photoresist spin-coating while saving time and labor.

Abstract: A neural network processing method, a neural network processing unit (NPU) and a processing device are provided. The method includes: obtaining by a quantizing unit in the NPU float type input data, quantizing the float type input data to obtain quantized input data, and providing the quantized input data to an operation unit; performing by the operation unit of the NPU a matrix-vector operation and/or a convolution operation to the quantized input data to obtain an operation result of the quantized input data; and performing by the quantizing unit inverse quantization to the operation result output by the operation unit to obtain an inverse quantization result.

Abstract: The present application discloses a voice processing system and method, an electronic device and a readable storage medium, which relates to the field of voice processing technologies. The voice processing system includes: a neural-network processing unit (NPU) and an RISC-V processor; wherein the RISC-V processor includes predefined NPU instructions, and the RISC-V processor is configured to send the NPU instructions to the NPU to cause the NPU to perform corresponding neural network computation; the NPU includes a memory unit and a computing unit, and the memory unit includes a plurality of storage groups; the computing unit is configured to execute one of main computation, special computation, auxiliary computation and complex instruction set computing (CISC) control according to the received NPU instructions.

Abstract: The present application discloses a memory control method, a controller, a chip and an electronic device, and relates to the field of control technology. A specific implementation solution is: obtaining first address information of an access to the memory performed by the processor within a first time window; determining, according to the first address information and an address jump relationship, a target slice of the memory that is to be accessed by the processor within a second time window; and controlling the target slice in the memory to be turned on and controlling a slice other than the target slice in the memory to be turned off within the second time window. Through the above-mentioned process, each slice is dynamically turned on and off according to the actual situation of memory access, thereby reducing the power consumption of the memory to the maximum extent.

Abstract: A data storing method includes: obtaining data to be stored and a start address of a currently available storage unit in the storage array, in which the start address comprises a start row, a start column and a start unit identifier; determining a data storage operation to be executed based on the start address and the data to be stored; and controlling a first interface in the storage array to write the data to be stored block by block in the same row into each storage unit of each storage block having the same identifier as the start unit identifier.

Abstract: The present disclosure discloses a speech chip and an electronic device. The speech chip includes a first processing module, a second processing module and a third processing module. The first processing module is configured to run an operating system, and to perform data scheduling on modules other than the first processing module in the chip. The second processing module is configured to perform a mutual conversion between speech and text based on a speech model. The third processing module is configured to perform digital signal processing on inputted speech.

Abstract: Embodiments of the present disclosure relate to a method and apparatus for processing information. The method may include: determining an instruction category of an instruction based on an instruction operation code of the acquired instruction, where the instruction category includes a dedicated instruction including register selection information, base address information, and a length of to-be-read data; sending, in response to determining that the instruction is the dedicated instruction, the dedicated instruction to a preset operator for the operator to perform following operation steps: selecting a configuration register group from preset configuration register groups as a target configuration register group according to the register selection information; reading configuration information from the target configuration register group based on the base address information and the length of the to-be-read data; performing a preset operation for the configuration information.

Abstract: The present application discloses a memory control method, a controller, a chip and an electronic device, and relates to the field of control technology. A specific implementation solution is: obtaining first address information of an access to the memory performed by the processor within a first time window; determining, according to the first address information and an address jump relationship, a target slice of the memory that is to be accessed by the processor within a second time window; and controlling the target slice in the memory to be turned on and controlling a slice other than the target slice in the memory to be turned off within the second time window. Through the above-mentioned process, each slice is dynamically turned on and off according to the actual situation of memory access, thereby reducing the power consumption of the memory to the maximum extent.

Abstract: The present disclosure proposes a speech chip and an electronic device. The speech chip includes: a peripheral interface connected to a speech receiver and configured to receive a speech signal; a bus matrix connected to the peripheral interface; a first processor connected to the bus matrix and configured to determine whether is the speech signal contains a wake-up word according to the speech signal; a second processor connected to the bus matrix and configured to perform signal denoising and speech recognition on the speech signal; and a memory array connected to the bus matrix.

Abstract: A spin coating device and method. The spin coating device includes a rotatable rotary shaft and sucker fixed on an end portion of the shaft, and an electromagnetic induction device below the sucker which includes an annular magnet fixed below the sucker, coil group formed by a first and second coil, and strip-shaped magnet fixed at the rotary shaft. A base on the sucker has a notch. The unbalanced centrifugal force during rotation of the sucker causes vibration. The electromagnetic induction device enables the centrifugal force generated during rotation of the sucker to be in balance with the magnetic force generated by the electromagnetic induction device to adjust the levelness of the sucker surface. The device does not need manual manipulation, enables the sucker to be more stable, reduces damage to the equipment due to vibration, and improves the effect of photoresist spin-coating while saving time and labor.

Abstract: An apparatus including a heat sink layer and a magnetic recording layer over the heat sink layer. In addition, a thermochromic layer is over the heat sink layer, wherein the thermochromic layer includes a first optical absorbance at a first temperature and a second optical absorbance at a second temperature.

Abstract: Provided herein is an apparatus including a head over-coat and a depleted region in the head over-coat. A media over-coat is deposited in the depleted region. A near field transducer is adjacent to the head over-coat, wherein the near field transducer combusts the deposited media over-coat.

Abstract: An apparatus including a heat sink layer and a magnetic recording layer over the heat sink layer. In addition, a thermochromic layer is over the heat sink layer, wherein the thermochromic layer includes a first optical absorbance at a first temperature and a second optical absorbance at a second temperature.

Abstract: Provided herein is an apparatus including a substrate and a magnetic recording layer over the substrate. In addition, a thermochromic layer is over the substrate, wherein the thermochromic layer includes a first optical absorbance at a first temperature and a second optical absorbance at a second temperature.

Abstract: Provided herein is an apparatus including a substrate and a magnetic recording layer over the substrate. In addition, a thermochromic layer is over the substrate, wherein the thermochromic layer includes a first optical absorbance at a first temperature and a second optical absorbance at a second temperature.