Patents by Inventor Xiaoqian Zhang

Xiaoqian Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11184928
    Abstract: A method includes: receiving, by a first access device, a random access message sent by user equipment; and sending, by the first access device, first system information to the user equipment based on the random access message, where the first system information includes cell reselection information related to the first access device. According to the present invention, cell reselection information can be transferred in a random access procedure.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: November 23, 2021
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Xiaoqian Jia, Haiyan Luo, Hongzhuo Zhang, Li Yang
  • Patent number: 11132296
    Abstract: The embodiments herein store tabulated values representing a linear or non-linear function in separate memory banks to reduce the size of memory used to store the tabulated values while being able to provide upper and lower values for performing linear interpolation in parallel (e.g., the same cycle). To do so, a linear interpolation system includes a first memory bank that stores the even indexed tabulated values while a second memory bank stores the odd indexed tabulated values. During each clock cycle, the first and second memory banks can output upper and lower values for linear interpolation (although which memory bank outputs the upper value and which outputs the lower value can vary). Using the upper and lower values, the linear interpolation system performs linear interpolation to approximate the value of a non-linear function that is between the upper and lower values.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: September 28, 2021
    Assignee: XILINX, INC.
    Inventors: Ephrem C. Wu, Xiaoqian Zhang
  • Patent number: 11127442
    Abstract: An integrated circuit (IC) includes a plurality of dies. The IC includes a plurality of memory channel interfaces configured to communicate with a memory, wherein the plurality of memory channel interfaces are disposed within a first die of the plurality of dies. The IC may include a compute array distributed across the plurality of dies and a plurality of remote buffers distributed across the plurality of dies. The plurality of remote buffers are coupled to the plurality of memory channels and to the compute array. The IC further includes a controller configured to determine that each of the plurality of remote buffers has data stored therein and, in response, broadcast a read enable signal to each of the plurality of remote buffers initiating data transfers from the plurality of remote buffers to the compute array across the plurality of dies.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: September 21, 2021
    Assignee: Xilinx, Inc.
    Inventors: Xiaoqian Zhang, Ephrem C. Wu, David Berman
  • Publication number: 20210174848
    Abstract: An integrated circuit (IC) includes a plurality of dies. The IC includes a plurality of memory channel interfaces configured to communicate with a memory, wherein the plurality of memory channel interfaces are disposed within a first die of the plurality of dies. The IC may include a compute array distributed across the plurality of dies and a plurality of remote buffers distributed across the plurality of dies. The plurality of remote buffers are coupled to the plurality of memory channels and to the compute array. The IC further includes a controller configured to determine that each of the plurality of remote buffers has data stored therein and, in response, broadcast a read enable signal to each of the plurality of remote buffers initiating data transfers from the plurality of remote buffers to the compute array across the plurality of dies.
    Type: Application
    Filed: December 6, 2019
    Publication date: June 10, 2021
    Applicant: Xilinx, Inc.
    Inventors: Xiaoqian Zhang, Ephrem C. Wu, David Berman
  • Patent number: 10673438
    Abstract: A digital signal processor (DSP) slice is disclosed. The DSP slice includes an input stage to receive a plurality of input signals, a pre-adder coupled to the input stage and configured to perform one or more operations on one or more of the plurality of input signals, and a multiplier coupled to the input stage and the pre-adder and configured to perform one or more multiplication operations on one or more of the plurality of input signals or the output of the pre-adder. The DSP slice further includes an arithmetic logic unit (ALU) coupled to the input stage, the pre-adder, and the multiplier. The ALU is configured to perform one or more mathematical or logical operations on one or more of the plurality of input signals, the output of the pre-adder, or the output of the multiplier.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: June 2, 2020
    Assignee: XILINX, INC.
    Inventors: Adam Elkins, Ephrem C. Wu, John M. Thendean, Adnan Pratama, Yashodhara Parulkar, Xiaoqian Zhang
  • Publication number: 20200026989
    Abstract: A circuit arrangement includes an array of MAC circuits, wherein each MAC circuit includes a cache configured for storage of a plurality of kernels. The MAC circuits are configured to receive a first set of data elements of an IFM at a first rate. The MAC circuits are configured to perform first MAC operations on the first set of the data elements and a first one of the kernels associated with a first OFM depth index during a first MAC cycle, wherein a rate of MAC cycles is faster than the first rate. The MAC circuits are configured to perform second MAC operations on the first set of the data elements and a second one of the kernels associated with a second OFM depth index during a second MAC cycle that consecutively follows the first MAC cycle.
    Type: Application
    Filed: July 19, 2018
    Publication date: January 23, 2020
    Applicant: Xilinx, Inc.
    Inventors: Xiaoqian Zhang, Ephrem C. Wu, David Berman
  • Patent number: 10346093
    Abstract: Disclosed circuitry includes RAM circuits, a memory controller, and an array of processing circuits. Each RAM circuit includes a read port and a write port. The memory controller accesses tensor data arranged in banks of tensor buffers in the RAM circuits. The memory controller is coupled to each read port by shared read control signal lines and to each write port by shared write control signal lines. The memory controller generates read control and write control signals for accessing different ones of the tensor buffers at different times. The array of processing circuits is coupled to one of the RAM circuits. The array includes multiple rows and multiple of columns of processing circuits for performing tensor operations on the tensor data. The processing circuits in each row in each array of processing circuits are coupled to input the same tensor data.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: July 9, 2019
    Assignee: XILINX, INC.
    Inventors: Ephrem C. Wu, Xiaoqian Zhang, David Berman
  • Patent number: 9896474
    Abstract: (3?,9?,10?,13?,14?,17?,20S,22E)-Ergosta-5,7,22-trien-3-ol. A method for preparing the same by drying a fruiting body of Cordyceps militaris, grinding the fruiting body to yield ultrafine powders; boiling and extracting the ultrafine powders, centrifuging and collecting a precipitate. A method for treating a tumor by administering to a patient in need of treating a tumor (3?,9?,10?,13?,14?,17?,20S,22E)-ergosta-5,7,22-trien-3-ol.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: February 20, 2018
    Assignee: ZHENGYUANTANG (TIANJIN BINHAI NEW AREA) BIOTECH CO., LTD.
    Inventors: Yaozhou Zhang, Jiachen Sun, Lei Jiang, Jian Zhang, Yujiao Chen, Xiaoqian Zhang, Simiao Du, Pengai Gu, Jinsong Cui
  • Patent number: 9779786
    Abstract: A system includes global memory circuitry configured to store input tensors and output tensors. Row data paths are each connected to an output port of the memory circuitry. Column data paths are connected to an input port of the memory circuitry. Processing elements are arranged in rows and columns along the row data paths and column data paths, respectively. The processing elements include local memory circuitry configured to store multiple masks and processing circuitry. The processing circuitry is configured to receive portions of the input tensors from one of the row data paths; receive masks from the local memory circuitry; perform multiple tensor operations on a same received portion of an input tensors by applying a different retrieved mask for each tensor operation; and generate, using results of the multiple tensor operations, an output for a corresponding column data path.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: October 3, 2017
    Assignee: XILINX, INC.
    Inventors: Ephrem C. Wu, Inkeun Cho, Xiaoqian Zhang
  • Publication number: 20160340383
    Abstract: (3?,9?,10?,13?,14?,17?,20S,22E)-Ergosta-5,7,22-trien-3-ol. A method for preparing the same by drying a fruiting body of Cordyceps militaris, grinding the fruiting body to yield ultrafine powders; boiling and extracting the ultrafine powders, centrifuging and collecting a precipitate. A method for treating a tumor by administering to a patient in need of treating a tumor (3?,9?,10?,13?,14?,17?,20S,22E)-ergosta-5,7,22-trien-3-ol.
    Type: Application
    Filed: August 3, 2016
    Publication date: November 24, 2016
    Inventors: Yaozhou ZHANG, Jiachen SUN, Lei JIANG, Jian ZHANG, Yujiao CHEN, Xiaoqian ZHANG, Simiao DU, Pengai GU, Jinsong CUI
  • Patent number: 9460007
    Abstract: An apparatus relates generally to time sharing of an arithmetic unit. In such an apparatus, a controller is coupled to provide read pointers and write pointers. A memory block is coupled to receive the read pointers and the write pointers. A selection network is coupled to the memory block and the arithmetic unit. The memory block includes a write-data network, a read-data network, and memory banks.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: October 4, 2016
    Assignee: XILINX, INC.
    Inventors: Ephrem C. Wu, Xiaoqian Zhang
  • Patent number: 9355696
    Abstract: In an example, a control device includes a data path, a clock path, a multiplexing circuit, and a calibration unit. The data path comprises a data delay unit coupled to a data input of a sampling circuit. The clock path comprises a clock delay unit coupled to a clock input of the sampling circuit. The multiplexing circuit selectively couples a reference clock or a data bus to an input of the data delay unit, and selectively couples the reference clock or a source clock to an input of the clock delay unit. The calibration unit is coupled to a data output of the sampling circuit. The calibration unit is operable to adjust delay values of the data delay unit and the clock delay unit based on the data output of the sampling circuit to establish and maintain a relative delay between the data path and the clock path.
    Type: Grant
    Filed: November 6, 2014
    Date of Patent: May 31, 2016
    Assignee: XILINX, INC.
    Inventors: Terence J. Magee, Xiaoqian Zhang
  • Publication number: 20160133305
    Abstract: In an example, a control device includes a data path, a clock path, a multiplexing circuit, and a calibration unit. The data path comprises a data delay unit coupled to a data input of a sampling circuit. The clock path comprises a clock delay unit coupled to a clock input of the sampling circuit. The multiplexing circuit selectively couples a reference clock or a data bus to an input of the data delay unit, and selectively couples the reference clock or a source clock to an input of the clock delay unit. The calibration unit is coupled to a data output of the sampling circuit. The calibration unit is operable to adjust delay values of the data delay unit and the clock delay unit based on the data output of the sampling circuit to establish and maintain a relative delay between the data path and the clock path.
    Type: Application
    Filed: November 6, 2014
    Publication date: May 12, 2016
    Applicant: XILINX, INC.
    Inventors: Terence J. Magee, Xiaoqian Zhang
  • Patent number: 9331701
    Abstract: A data interface enabling the calibration of input data comprises a first data receiver having a first plurality of input data lines coupled to receive a corresponding first plurality of data bits associated with a data bus, the first data receiver having a first control circuit enabling calibration of the first plurality of input data lines; and a second data receiver having a second plurality of input data lines coupled to receive a corresponding second plurality of data bits associated with the data bus, the second data receiver having a second control circuit enabling calibration of the second plurality of data lines. The first plurality of input data lines of the first data receiver are calibrated in parallel with the second plurality of input data lines of the second data receiver.
    Type: Grant
    Filed: June 11, 2014
    Date of Patent: May 3, 2016
    Assignee: XILINX, INC.
    Inventors: Xiaoqian Zhang, Terence Magee
  • Patent number: 8861669
    Abstract: The present disclosure provides techniques for recovering source stream clock data at the sink in a high definition multimedia digital content transport system. The disclosure includes a fractional-N Phase-Locked Loop (PLL) based clock generator, a programmable Sigma-Delta Modulator (SDM), and a clock data calibrator to fully recover the original source stream clock data. The fractional-N PLL provides flexible source stream clock recovery. When there is a frequency deviation between the original clock and the regenerated clock, the clock data calibrator control circuit adjusts the clock data, preventing any stream data buffer overflow or underflow problems. The disclosed techniques are compatible with the sink devices based on the standards of DisplayPort and HDMI.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: October 14, 2014
    Assignee: Synaptics Incorporated
    Inventors: Xiaoqian Zhang, Shubing Zhai, Yanbo Wang
  • Patent number: 8531352
    Abstract: A multi-monitor display driver that provides consolidated EDID data is provided. The display driver reads the EDID data from the one or more monitors coupled to the driver, determines a consolidated EDID data that is compatible with each of the monitors, and writes the EDID data to an EDID memory in the driver. A source interacting with the driver reads the consolidated EDID data to control interactions with the driver.
    Type: Grant
    Filed: June 15, 2010
    Date of Patent: September 10, 2013
    Assignee: Synaptics Incorporated
    Inventors: Henry Zeng, Jing Qian, Xiaoqian Zhang, Xuexin Liu
  • Patent number: 8422518
    Abstract: A method of transmitting audio data across a digital interface is provided. The method includes receiving audio data, organized as a plurality of audio samples. At least one of the plurality of audio samples may be placed into a data packet. The data packet may be transmitted during a valid transmission interval if the data packet is full or during a valid transmission interval in response to receiving a packet send event.
    Type: Grant
    Filed: August 19, 2008
    Date of Patent: April 16, 2013
    Assignee: Integrated Device Technology, inc.
    Inventors: Zhiyong Guan, Xiaoqian Zhang, Qi Li
  • Patent number: 8217689
    Abstract: A method and a circuit are described for recovery of video clocks for a DisplayPort receiver. The disclosure includes two clock dividers, a direct digital synthesis (DDS), a fixed multiplier Phase-Locked Loop (PLL) on a DisplayPort video system. A DisplayPort receiver link clock is divided to a lower frequency as the input of the DDS which can lower the performance requirement on a DDS circuit. The output from a time stamp value indirectly controls a direct digital synthesis device, which then drives a PLL to generate the recovery clock signal. The technique is suitable for implementation on an integrated circuit and Field Programmable Gate array system.
    Type: Grant
    Filed: January 19, 2010
    Date of Patent: July 10, 2012
    Assignee: Integrated Device Technology, Inc.
    Inventors: Lu Yang, Sibing Wang, Xiaoqian Zhang
  • Patent number: 8095707
    Abstract: A method and apparatus for synchronizing I/O peripherals with a CPU in an embedded system is discussed. The method involves receiving an address from the CPU in response to a read and/or write access, translating the address received from the CPU to identify a I/O peripheral to be accessed, disabling the operation of the CPU and synchronizing a memory from the CPU clock domain to the clock domain of the identified I/O peripheral. Upon completion of the read/write access, the identified I/O peripheral sends an acknowledgment, the memory is then synchronized from the clock domain of the I/O peripheral to the CPU clock domain and the operation of the CPU is then enabled. In another embodiment, if the acknowledgement from the identified I/O peripheral is not received within a predefined time duration, reserved data is sent to the CPU and the operation/access can be restarted.
    Type: Grant
    Filed: August 19, 2008
    Date of Patent: January 10, 2012
    Assignee: Integrated Device Technology, inc.
    Inventors: Xiaoqian Zhang, Zhiyong Guan, Qi Li
  • Publication number: 20110310070
    Abstract: A multi-monitor display driver that splits a received video image into multiple images for display on separate monitors. The driver includes a line buffer where data from a received image is written. Monitor interfaces can receive data from a portion of the line buffer corresponding to the interface to split the image.
    Type: Application
    Filed: June 14, 2011
    Publication date: December 22, 2011
    Inventors: Henry ZENG, Jing QIAN, Xiaoqian ZHANG, Xuexin LIU