Abstract: A temperature detection circuit is provided. The temperature detection circuit includes an enable signal generation module and a detection output module. The enable signal generation module is configured to segmentally generate four detection enable signals. The detection output module is connected to an output terminal of the enable signal generation module, and is configured to segmentally generate four thresholds based on the four detection enable signals, and sequentially compare the four thresholds with a detection value. A charging-prohibited signal is valid when a low temperature protection or a high temperature protection is triggered, and a charging-prohibited/discharging-prohibited signal is valid when an ultra-low temperature protection or an ultra-high temperature protection is triggered.

Abstract: An anchoring device for adapting to tide level for a wave energy power generation device comprises: a housing, wherein a central main shaft is provided at the center thereof, two ends of the central main shaft are respectively rigidly connected to a volute spring, and the interior of the housing is divided into several independent compartments, including a central compartment accommodating the central main shaft; a shaft lock and a central main gear capable of driving the central main shaft to rotate mounted on the central main shaft; and a plurality of hoisting wheel compartments arranged at equal intervals in a circumferential array around the central main shaft. A hoisting wheel is provided in each of the hoisting wheel compartments, and an anchor chain wound on the hoisting wheel protrudes out of the housing through an opening at the bottom of the hoisting wheel compartment.

Abstract: An anchoring device for adapting to tide level for a wave energy power generation device comprises: a housing, wherein a central main shaft is provided at the center thereof, two ends of the central main shaft are respectively rigidly connected to a volute spring, and the interior of the housing is divided into several independent compartments, including a central compartment accommodating the central main shaft; a shaft lock and a central main gear capable of driving the central main shaft to rotate mounted on the central main shaft; and a plurality of hoisting wheel compartments arranged at equal intervals in a circumferential array around the central main shaft. A hoisting wheel is provided in each of the hoisting wheel compartments, and an anchor chain wound on the hoisting wheel protrudes out of the housing through an opening at the bottom of the hoisting wheel compartment.

Abstract: An active rectifier bridge circuit and an on-chip integrated system. The active rectifier bridge circuit includes: a bias module, configured to provide a first bias current source, a second bias current source, and an internal power supply for a gate driver module; the gate driver module controlled by the first bias current source, the second bias current source, and the internal power supply, and configured to process one group of alternating current input voltages to generate two groups of control signals that are mutually inverted, to generate four gate drive signals; a power switch tube rectification module, connected to the bias module and the gate driver module, configured to: perform a turn-on or turn-off operation on corresponding power switch tubes under the control of the four gate drive signals, and convert the one group of alternating current input voltages into a direct current output voltage for output.

Abstract: An active rectifier bridge circuit and an on-chip integrated system. The active rectifier bridge circuit includes: a bias module, configured to provide a first bias current source, a second bias current source, and an internal power supply for a gate driver module; the gate driver module controlled by the first bias current source, the second bias current source, and the internal power supply, and configured to process one group of alternating current input voltages to generate two groups of control signals that are mutually inverted, to generate four gate drive signals; a power switch tube rectification module, connected to the bias module and the gate driver module, configured to: perform a turn-on or turn-off operation on corresponding power switch tubes under the control of the four gate drive signals, and convert the one group of alternating current input voltages into a direct current output voltage for output.

Abstract: A method for forming layers suitable for a V-NAND stack is disclosed. Specifically, the method may include multiple cycles for forming an oxide and a nitride in order to form an oxynitride layer.

Abstract: A method for forming layers suitable for a V-NAND stack is disclosed. Specifically, the method may include multiple cycles for forming an oxide and a nitride in order to form an oxynitride layer.

Abstract: In some embodiments, a semiconductor surface may be effectively passivated by nitridation, preferably using hydrazine, a hydrazine derivative, or a combination thereof. The surface may be the semiconductor surface of a transistor channel region. In some embodiments, native oxide is removed from the semiconductor surface and the surface is subsequently nitrided. In some other embodiments, a semiconductor surface oxide layer is formed at the semiconductor surface and the passivation is accomplished by forming a semiconductor oxynitride layer at the surface, with the nitridation contributing nitrogen to the surface oxide to form the oxynitride layer. The semiconductor oxide layer may be deposited by atomic layer deposition (ALD) and the nitridation may also be conducted as part of the ALD.

Abstract: A system and a method for passivating a surface of a semiconductor. The method includes providing the surface of the semiconductor to a reaction chamber of a reactor, exposing the surface of the semiconductor to a gas-phase metal containing precursor in the reaction chamber and exposing the surface of the semiconductor to a gas-phase chalcogenide containing precursor. The methods also include passivating the surface of the semiconductor using the gas-phase metal containing precursor and the gas-phase chalcogenide containing precursor to form a passivated surface.

Abstract: A method for forming layers suitable for a V-NAND stack is disclosed. Specifically, the method may include multiple cycles for forming an oxide and a nitride in order to form an oxynitride layer.

Abstract: A system and a method for passivating a surface of a semiconductor. The method includes providing the surface of the semiconductor to a reaction chamber of a reactor, exposing the surface of the semiconductor to a gas-phase metal containing precursor in the reaction chamber and exposing the surface of the semiconductor to a gas-phase chalcogenide containing precursor. The methods also include passivating the surface of the semiconductor using the gas-phase metal containing precursor and the gas-phase chalcogenide containing precursor to form a passivated surface.

Abstract: Improved methods and systems for passivating a surface of a high-mobility semiconductor and structures and devices formed using the methods are disclosed. The method includes providing a high-mobility semiconductor surface to a chamber of a reactor and exposing the high-mobility semiconductor surface to a gas-phase chalcogen precursor to passivate the high-mobility semiconductor surface.

Abstract: A method for forming layers suitable for a V-NAND stack is disclosed. Specifically, the method may include multiple cycles for forming an oxide and a nitride in order to form an oxynitride layer.

Abstract: Improved methods and systems for passivating a surface of a high-mobility semiconductor and structures and devices formed using the methods are disclosed. The method includes providing a high-mobility semiconductor surface to a chamber of a reactor and exposing the high-mobility semiconductor surface to a gas-phase chalcogen precursor to passivate the high-mobility semiconductor surface.

Abstract: A method for depositing a thin film onto a substrate is disclosed. In particular, the method forms a transitional metal silicate onto the substrate. The transitional metal silicate may comprise a lanthanum silicate or yttrium silicate, for example. The transitional metal silicate indicates reliability as well as good electrical characteristics for use in a gate dielectric material.

Abstract: In some embodiments, a semiconductor surface may be effectively passivated by nitridation, preferably using hydrazine, a hydrazine derivative, or a combination thereof. The surface may be the semiconductor surface of a transistor channel region. In some embodiments, native oxide is removed from the semiconductor surface and the surface is subsequently nitrided. In some other embodiments, a semiconductor surface oxide layer is formed at the semiconductor surface and the passivation is accomplished by forming a semiconductor oxynitride layer at the surface, with the nitridation contributing nitrogen to the surface oxide to form the oxynitride layer. The semiconductor oxide layer may be deposited by atomic layer deposition (ALD) and the nitridation may also be conducted as part of the ALD.