Abstract: A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a source electrode, a drain electrode, a gate electrode, and a third nitride-based semiconductor layer. The first nitride-based semiconductor layer has at least one trench. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and spaced apart from the trench. The source electrode and the drain electrode are disposed above the second nitride-based semiconductor layer. The gate electrode is disposed above the second nitride-based semiconductor layer and between the source and drain electrodes, so as to at least define a drift region between the gate electrode and the drain electrode and overlaps with the trench. The third nitride-based semiconductor layer is at least disposed in the trench and extends upward from the trench to make contact with the second nitride-based semiconductor layer.

Abstract: A semiconductor device includes a first and a second nitride-based semiconductor layers, a gate electrode, a first and a second field plates, and a first dielectric layer. The first field plate is disposed above the second nitride-based semiconductor layer. The second field plate is discontinuous and disposed above the second nitride-based semiconductor layer and in a position higher than the first field plate. The second field plate includes one or more enclosed discontinuities in a discontinuity region thereof. The first dielectric layer is disposed above the second field plate. The first dielectric layer covers and penetrates the second discontinuous field plate in the discontinuity region such that the second field plate encloses at least one portion of the first dielectric layer within its one or more enclosed discontinuities.

Abstract: A nitride-based semiconductor device includes a first and a second nitride-based semiconductor layers, a doped III-V semiconductor layer, a gate, a source electrode, and a drain electrode. The doped III-V semiconductor layer is disposed over the second nitride-based semiconductor layer and has opposite first sidewalls which recessed inward toward a body of the doped III-V semiconductor layer between the sidewalls to make a curved profile located at a bottom of the doped III-V semiconductor layer. The gate electrode is disposed above the doped III-V semiconductor layer. The source electrode and the drain electrode are disposed above the second nitride-based semiconductor layer. The gate electrode is located between the source and drain electrodes.