Patents by Inventor Xiaoqiu Huang

Xiaoqiu Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200350401
    Abstract: A semiconductor device includes a source region and a drain region of a first conductivity type, a body region of a second conductivity type between the source region and the drain region, a gate configured to control current through a channel of the body region, a drift zone of the first conductivity type between the body region and the drain region, a superjunction structure formed by a plurality of regions of the second conductivity type laterally spaced apart from one another by intervening regions of the drift zone, and a diffusion barrier structure disposed along sidewalls of the regions of the second conductivity type of the superjunction structure. The diffusion barrier structure includes alternating layers of Si and oxygen-doped Si and a Si capping layer on the alternating layers of Si and oxygen-doped Si.
    Type: Application
    Filed: July 16, 2020
    Publication date: November 5, 2020
    Inventors: Martin Poelzl, Robert Haase, Sylvain Leomant, Maximilian Roesch, Ravi Keshav Joshi, Andreas Meiser, Xiaoqiu Huang, Ling Ma
  • Patent number: 10790353
    Abstract: A semiconductor device includes a source region and a drain region of a first conductivity type, a body region of a second conductivity type between the source region and the drain region, a gate configured to control current through a channel of the body region, a drift zone of the first conductivity type between the body region and the drain region, a superjunction structure formed by a plurality of regions of the second conductivity type laterally spaced apart from one another by intervening regions of the drift zone, and a diffusion barrier structure disposed along sidewalls of the regions of the second conductivity type of the superjunction structure. The diffusion barrier structure includes alternating layers of Si and oxygen-doped Si and a Si capping layer on the alternating layers of Si and oxygen-doped Si.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: September 29, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Martin Poelzl, Robert Haase, Sylvain Leomant, Maximilian Roesch, Ravi Keshav Joshi, Andreas Meiser, Xiaoqiu Huang, Ling Ma
  • Publication number: 20200152733
    Abstract: A semiconductor device includes a source region and a drain region of a first conductivity type, a body region of a second conductivity type between the source region and the drain region, a gate configured to control current through a channel of the body region, a drift zone of the first conductivity type between the body region and the drain region, a superjunction structure formed by a plurality of regions of the second conductivity type laterally spaced apart from one another by intervening regions of the drift zone, and a diffusion barrier structure disposed along sidewalls of the regions of the second conductivity type of the superjunction structure. The diffusion barrier structure includes alternating layers of Si and oxygen-doped Si and a Si capping layer on the alternating layers of Si and oxygen-doped Si.
    Type: Application
    Filed: November 9, 2018
    Publication date: May 14, 2020
    Inventors: Martin Poelzl, Robert Haase, Sylvain Leomant, Maximilian Roesch, Ravi Keshav Joshi, Andreas Meiser, Xiaoqiu Huang, Ling Ma
  • Patent number: 8188543
    Abstract: An electronic device can include a substrate, a buried insulating layer overlying the substrate, and a semiconductor layer overlying the buried insulating layer, wherein the semiconductor layer is substantially monocrystalline. The electronic device can also include a conductive structure extending through the semiconductor layer and buried insulating layer and abutting the substrate, and an insulating spacer lying between the conductive structure and each of the semiconductor layer and the buried insulating layer.
    Type: Grant
    Filed: November 3, 2006
    Date of Patent: May 29, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Todd C. Roggenbauer, Vishnu K. Khemka, Ronghua Zhu, Amitava Bose, Paul Hui, Xiaoqiu Huang
  • Patent number: 7820519
    Abstract: A process of forming an electronic device can include providing a semiconductor-on-insulator substrate including a substrate, a first semiconductor layer, and a buried insulating layer lying between the first semiconductor layer and the substrate. The process can also include forming a field isolation region within the semiconductor layer, and forming an opening extending through the semiconductor layer and the buried insulating layer to expose the substrate. The process can further include forming a conductive structure within the opening, wherein the conductive structure abuts the substrate.
    Type: Grant
    Filed: November 3, 2006
    Date of Patent: October 26, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Todd C. Roggenbauer, Vishnu K. Khemka, Ronghua Zhu, Amitava Bose, Paul Hui, Xiaoqiu Huang, Van Wong
  • Patent number: 7645651
    Abstract: A method of forming a metal oxide semiconductor (MOS) device comprises defining an active area in an unstrained semiconductor layer structure, depositing a hard mask overlying the active area and a region outside of the active area, patterning the hard mask to expose the active area, selectively growing a strained semiconductor layer overlying the exposed active area, and forming a remainder of the MOS device. The active area includes a first doped region of first conductivity type and a second doped region of second conductivity type. The strained semiconductor layer provides a biaxially strained channel for the MOS device.
    Type: Grant
    Filed: December 6, 2007
    Date of Patent: January 12, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Xiaoqiu Huang, Veeraraghavan Dhandapani, Bich-Yen Nguyen, Amanda M. Kroll, Daniel T. Pham
  • Publication number: 20090146180
    Abstract: A method of forming a metal oxide semiconductor (MOS) device comprises defining an active area in an unstrained semiconductor layer structure, depositing a hard mask overlying the active area and a region outside of the active area, patterning the hard mask to expose the active area, selectively growing a strained semiconductor layer overlying the exposed active area, and forming a remainder of the MOS device. The active area includes a first doped region of first conductivity type and a second doped region of second conductivity type. The strained semiconductor layer provides a biaxially strained channel for the MOS device.
    Type: Application
    Filed: December 6, 2007
    Publication date: June 11, 2009
    Inventors: Xiaoqiu Huang, Veeraraghavan Dhandapani, Bich-Yen Nguyen, Amanda M. Kroll, Daniel T. Pham
  • Publication number: 20080124889
    Abstract: A process of forming an electronic device can include providing a semiconductor-on-insulator substrate including a substrate, a first semiconductor layer, and a buried insulating layer lying between the first semiconductor layer and the substrate. The process can also include forming a field isolation region within the semiconductor layer, and forming an opening extending through the semiconductor layer and the buried insulating layer to expose the substrate. The process can further include forming a conductive structure within the opening, wherein the conductive structure abuts the substrate.
    Type: Application
    Filed: November 3, 2006
    Publication date: May 29, 2008
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Todd C. ROGGENBAUER, Vishnu K. KHEMKA, Ronghua ZHU, Amitava BOSE, Paul HUI, Xiaoqiu HUANG, Van WONG
  • Publication number: 20080122025
    Abstract: An electronic device can include a substrate, a buried insulating layer overlying the substrate, and a semiconductor layer overlying the buried insulating layer, wherein the semiconductor layer is substantially monocrystalline. The electronic device can also include a conductive structure extending through the semiconductor layer and buried insulating layer and abutting the substrate, and an insulating spacer lying between the conductive structure and each of the semiconductor layer and the buried insulating layer.
    Type: Application
    Filed: November 3, 2006
    Publication date: May 29, 2008
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Todd C. Roggenbauer, Vishnu K. Khemka, Ronghua Zhu, Amitava Bose, Paul Hui, Xiaoqiu Huang