Patents by Inventor Xiaorong Morrow
Xiaorong Morrow has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8299617Abstract: Described is a method and apparatus for forming interconnects with a metal-metal oxide electromigration barrier and etch-stop. In one embodiment of the invention, the method includes depositing a metal layer on the top of a planarized interconnect layer, the interconnect layer having an interlayer dielectric (ILD) with a top that is planar with the top of an electrically conductive interconnect. In one embodiment of the invention, the method includes reacting the metal layer with the ILD to form a metal oxide layer on the top of the ILD. At the same time, the metal layer will not be significantly oxidized by the electrically conductive interconnect, thus forming a metal barrier on the electrically conductive interconnect to improve electromigration performance. The metal barrier and metal oxide layer together comprise a protective layer. A second ILD may be subsequently formed on the protective layer, and the protective layer may act an etch-stop during a subsequent etch of the second ILD.Type: GrantFiled: April 19, 2010Date of Patent: October 30, 2012Assignee: Intel CorporationInventors: Xiaorong Morrow, Jihperng Leu, Markus Kuhn, Jose A. Maiz
-
Publication number: 20100219529Abstract: Described is a method and apparatus for forming interconnects with a metal-metal oxide electromigration barrier and etch-stop. In one embodiment of the invention, the method includes depositing a metal layer on the top of a planarized interconnect layer, the interconnect layer having an interlayer dielectric (ILD) with a top that is planar with the top of an electrically conductive interconnect. In one embodiment of the invention, the method includes reacting the metal layer with the ILD to form a metal oxide layer on the top of the ILD. At the same time, the metal layer will not be significantly oxidized by the electrically conductive interconnect, thus forming a metal barrier on the electrically conductive interconnect to improve electromigration performance. The metal barrier and metal oxide layer together comprise a protective layer. A second ILD may be subsequently formed on the protective layer, and the protective layer may act an etch-stop during a subsequent etch of the second ILD.Type: ApplicationFiled: April 19, 2010Publication date: September 2, 2010Inventors: Xiaorong Morrow, Jihperng Leu, Markus Kuhn, Jose A. Maiz
-
Patent number: 7727892Abstract: Described is a method and apparatus for forming interconnects with a metal-metal oxide electromigration barrier and etch-stop. In one embodiment of the invention, the method includes depositing a metal layer on the top of a planarized interconnect layer, the interconnect layer having an interlayer dielectric (ILD) with a top that is planar with the top of an electrically conductive interconnect. In one embodiment of the invention, the method includes reacting the metal layer with the ILD to form a metal oxide layer on the top of the ILD. At the same time, the metal layer will not be significantly oxidized by the electrically conductive interconnect, thus forming a metal barrier on the electrically conductive interconnect to improve electromigration performance. The metal barrier and metal oxide layer together comprise a protective layer. A second ILD may be subsequently formed on the protective layer, and the protective layer may act an etch-stop during a subsequent etch of the second ILD.Type: GrantFiled: September 25, 2002Date of Patent: June 1, 2010Assignee: Intel CorporationInventors: Xiaorong Morrow, Jihperng Leu, Markus Kuhn, Jose A. Maiz
-
Patent number: 7456490Abstract: A method and structure for sealing porous dielectrics using silane coupling reagents is herein described. A sealant chain (silane coupling reagent) is formed from at least silicon, carbon, oxygen, and hydrogen and exposed to a porous dielectric material, wherein the sealant chain reacts with a second chain, that has at least oxygen and is present in the porous dielectric defining the pores, to form a continuous layer over the surface of the porous dielectric.Type: GrantFiled: September 5, 2006Date of Patent: November 25, 2008Assignee: Intel CorporationInventors: Grant Kloster, Chih-I Wu, Xiaorong Morrow
-
Patent number: 7339271Abstract: Described is a method and apparatus for forming interconnects with a metal-metal oxide electromigration barrier and etch-stop. In one embodiment of the invention, the method includes depositing a metal layer on the top of a planarized interconnect layer, the interconnect layer having an interlayer dielectric (ILD) with a top that is planar with the top of an electrically conductive interconnect. In one embodiment of the invention, the method includes reacting the metal layer with the ILD to form a metal oxide layer on the top of the ILD. At the same time, the metal layer will not be significantly oxidized by the electrically conductive interconnect, thus forming a metal barrier on the electrically conductive interconnect to improve electromigration performance. The metal barrier and metal oxide layer together comprise a protective layer. A second ILD may be subsequently formed on the protective layer, and the protective layer may act an etch-stop during a subsequent etch of the second ILD.Type: GrantFiled: June 3, 2004Date of Patent: March 4, 2008Assignee: Intel CorporationInventors: Xiaorong Morrow, Jihperng Leu, Markus Kuhn, Jose A. Maiz
-
Publication number: 20070066079Abstract: A method and structure for sealing porous dielectrics using silane coupling reagents is herein described. A sealant chain (silane coupling reagent) is formed from at least silicon, carbon, oxygen, and hydrogen and exposed to a porous dielectric material, wherein the sealant chain reacts with a second chain, that has at least oxygen and is present in the porous dielectric defining the pores, to form a continuous layer over the surface of the porous dielectric.Type: ApplicationFiled: September 5, 2006Publication date: March 22, 2007Inventors: Grant Kloster, Chih-I Wu, Xiaorong Morrow
-
Patent number: 7122481Abstract: A method and structure for sealing porous dielectrics using silane coupling reagents is herein described. A sealant chain (silane coupling reagent) is formed from at least silicon, carbon, oxygen, and hydrogen and exposed to a porous dielectric material, wherein the sealant chain reacts with a second chain, that has at least oxygen and is present in the porous dielectric defining the pores, to form a continuous layer over the surface of the porous dielectric.Type: GrantFiled: July 25, 2003Date of Patent: October 17, 2006Assignee: Intel CorporationInventors: Grant Kloster, Chih-I Wu, Xiaorong Morrow
-
Publication number: 20050020074Abstract: A method and structure for sealing porous dielectrics using silane coupling reagents is herein described. A sealant chain (silane coupling reagent) is formed from at least silicon, carbon, oxygen, and hydrogen and exposed to a porous dielectric material, wherein the sealant chain reacts with a second chain, that has at least oxygen and is present in the porous dielectric defining the pores, to form a continuous layer over the surface of the porous dielectric.Type: ApplicationFiled: July 25, 2003Publication date: January 27, 2005Inventors: Grant Kloster, Chih-I Wu, Xiaorong Morrow
-
Publication number: 20040224515Abstract: Described is a method and apparatus for forming interconnects with a metal-metal oxide electromigration barrier and etch-stop. In one embodiment of the invention, the method includes depositing a metal layer on the top of a planarized interconnect layer, the interconnect layer having an interlayer dielectric (ILD) with a top that is planar with the top of an electrically conductive interconnect. In one embodiment of the invention, the method includes reacting the metal layer with the ILD to form a metal oxide layer on the top of the ILD. At the same time, the metal layer will not be significantly oxidized by the electrically conductive interconnect, thus forming a metal barrier on the electrically conductive interconnect to improve electromigration performance. The metal barrier and metal oxide layer together comprise a protective layer. A second ILD may be subsequently formed on the protective layer, and the protective layer may act an etch-stop during a subsequent etch of the second ILD.Type: ApplicationFiled: June 3, 2004Publication date: November 11, 2004Inventors: Xiaorong Morrow, Jihperng Leu, Markus Kuhn, Jose A. Maiz
-
Patent number: 6794755Abstract: Described is a method and apparatus for altering the top surface of a metal interconnect. In one embodiment of the invention, a metal interconnect and a barrier layer are formed into an interlayer dielectric (ILD) and the metal interconnect and the barrier layer are planarized to the top of the ILD. The top surfaces of the metal interconnect, the barrier layer, and the ILD are altered with a second metal to form an electromigration barrier. In one embodiment of the invention, the second metal is prevented from contaminating the electrical resistivity of the metal interconnect.Type: GrantFiled: March 25, 2003Date of Patent: September 21, 2004Assignee: Intel CorporationInventors: Jose A. Maiz, Xiaorong Morrow, Thomas Marieb, Carolyn Block, Jihperng Leu, Paul McGregor, Markus Kuhn, Mitchell C. Taylor
-
Publication number: 20040102031Abstract: A low-k dielectric sacrificial material is formed within a microelectronic structure covered with a suitable porous or low density permeable material. At an appropriate time, the underlying sacrificial material is decomposed and diffused away through the overlying permeable material. As a result, at least one void is created, contributing to desirable dielectric characteristics.Type: ApplicationFiled: November 21, 2002Publication date: May 27, 2004Inventors: Grant M. Kloster, Xiaorong Morrow, Jihperng Leu
-
Publication number: 20040058547Abstract: Described is a method and apparatus for forming interconnects with a metal-metal oxide electromigration barrier and etch-stop. In one embodiment of the invention, the method includes depositing a metal layer on the top of a planarized interconnect layer, the interconnect layer having an interlayer dielectric (ILD) with a top that is planar with the top of an electrically conductive interconnect. In one embodiment of the invention, the method includes reacting the metal layer with the ILD to form a metal oxide layer on the top of the ILD. At the same time, the metal layer will not be significantly oxidized by the electrically conductive interconnect, thus forming a metal barrier on the electrically conductive interconnect to improve electromigration performance. The metal barrier and metal oxide layer together comprise a protective layer. A second ILD may be subsequently formed on the protective layer, and the protective layer may act an etch-stop during a subsequent etch of the second ILD.Type: ApplicationFiled: September 25, 2002Publication date: March 25, 2004Inventors: Xiaorong Morrow, Jihperng Leu, Markus Kuhn, Jose A. Maiz
-
Publication number: 20040056366Abstract: Described is a method and apparatus for altering the top surface of a metal interconnect. In one embodiment of the invention, a metal interconnect and a barrier layer are formed into an interlayer dielectric (ILD) and the metal interconnect and the barrier layer are planarized to the top of the ILD. The top surfaces of the metal interconnect, the barrier layer, and the ILD are altered with a second metal to form an electromigration barrier. In one embodiment of the invention, the second metal is prevented from contaminating the electrical resistivity of the metal interconnect.Type: ApplicationFiled: September 25, 2002Publication date: March 25, 2004Inventors: Jose A. Maiz, Xiaorong Morrow, Thomas Marieb, Carolyn Block, Jihperng Leu, Paul McGregor, Markus Kuhn, Mitchell C. Taylor
-
Publication number: 20040056329Abstract: Described is a method and apparatus for altering the top surface of a metal interconnect. In one embodiment of the invention, a metal interconnect and a barrier layer are formed into an interlaver dielectric (ILD) and the metal interconnect and the barrier layer are planarized to the top of the ILD. The top surfaces of the metal interconnect, the barrier layer, and the ILD are altered with a second metal to form an electromigration barrier. In one embodiment of the invention, the second metal is prevented from contaminating the electrical resistivity of the metal interconnect.Type: ApplicationFiled: March 25, 2003Publication date: March 25, 2004Inventors: Jose A. Maiz, Xiaorong Morrow, Thomas Marieb, Carolyn Block, Jihperng Leu, Paul McGregor, Markus Kuhn, Mitchell C. Taylor
-
Patent number: 6661094Abstract: A semiconductor device and an improved method for making it are described. The semiconductor device comprises a dual damascene interconnect that includes a conductive line. The device further includes a support structure that is spaced from the conductive line, and an insulating layer that is formed on the support structure and the conductive line. In the method for forming that device, a support structure is formed on a substrate, and an insulating layer is formed adjacent to it. Portions of the insulating layer are removed to form a via and a trench, which are filled with a conductive material to generate a dual damascene interconnect that includes a conductive line, wherein the conductive line is spaced from the support structure.Type: GrantFiled: June 25, 2002Date of Patent: December 9, 2003Assignee: Intel CorporationInventors: Patrick Morrow, Xiaorong Morrow
-
Publication number: 20020140104Abstract: A semiconductor device and an improved method for making it are described. The semiconductor device comprises a dual damascene interconnect that includes a conductive line. The device further includes a support structure that is spaced from the conductive line, and an insulating layer that is formed on the support structure and the conductive line. In the method for forming that device, a support structure is formed on a substrate, and an insulating layer is formed adjacent to it. Portions of the insulating layer are removed to form a via and a trench, which are filled with a conductive material to generate a dual damascene interconnect that includes a conductive line, wherein the conductive line is spaced from the support structure.Type: ApplicationFiled: March 27, 2001Publication date: October 3, 2002Inventors: Patrick Morrow, Xiaorong Morrow
-
Patent number: 6448177Abstract: A semiconductor device and an improved method for making it are described. The semiconductor device comprises a dual damascene interconnect that includes a conductive line. The device further includes a support structure that is spaced from the conductive line, and an insulating layer that is formed on the support structure and the conductive line. In the method for forming that device, a support structure is formed on a substrate, and an insulating layer is formed adjacent to it. Portions of the insulating layer are removed to form a via and a trench, which are filled with a conductive material to generate a dual damascene interconnect that includes a conductive line, wherein the conductive line is spaced from the support structure.Type: GrantFiled: March 27, 2001Date of Patent: September 10, 2002Assignee: Intle CorporationInventors: Patrick Morrow, Xiaorong Morrow