Patents by Inventor Xiaoru Sun

Xiaoru Sun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170288047
    Abstract: A shallow-trench semi-super-junction VDMOS device and a manufacturing method thereof are disclosed. According to an example of the present invention, the shallow-trench semi-super-junction VDMOS device includes: a substrate of a first conduction type; a first epitaxial layer over the substrate; a second epitaxial layer over the first epitaxial layer; two trench regions on both sides of the second epitaxial layer and extending from an upper surface to a bottom of the second epitaxial layer; a third epitaxial layer of a second conduction type formed in each of the trench regions; a fourth epitaxial layer over the second epitaxial layer; and well regions implanted from both sides of the upper surface of the fourth epitaxial layer and connected with the third epitaxial layers in the two trench regions. The present invention gives consideration to the cost of technical process and the convenience of production.
    Type: Application
    Filed: December 31, 2014
    Publication date: October 5, 2017
    Applicant: WUXI CHINA RESOURCES HUAJING MICROELETRONICS CO., LTD
    Inventors: Hongwei Zhou, Xiaoru Sun, Mengbo Ruan
  • Publication number: 20170236930
    Abstract: The present invention provides a vertical double-diffused metal-oxide semiconductor field-effect transistor and a manufacturing method. The manufacturing method comprises: providing a substrate of a first conductive type; growing a first epitaxial layer of the first conductive type above the substrate; forming column regions of the first conductive type and column regions of a second conductive type spaced in a staggered manner above the first epitaxial layer; forming a third epitaxial layer of the first conductive type above the column regions of the first conductive type, and forming a well region of the second conductive type above the column regions of the second conductive type; forming a gate region on a surface of the third epitaxial layer; forming a source region of the first conductive type in the well region of the second conductive type; and forming a gate metal layer, a source metal layer, and a drain metal layer.
    Type: Application
    Filed: December 31, 2014
    Publication date: August 17, 2017
    Applicant: WUXI CHINA RESOURCES HUAJING MICROELECTRONICS CO
    Inventors: Xiaoru Sun, Hongwei Zhou, Mengbo Ruan