Patents by Inventor Xiaoshan Shi

Xiaoshan Shi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11965029
    Abstract: Described herein are compositions and methods related to antigen binding proteins that bind to human ST2, including antibodies. In particular embodiments, the disclosure provides fully human anti-ST2 antibodies and deriviatives and variants thereof. Further provided are nucleic acids encoding such antibodies and antibody fragments, variants, and derivatives. Also, provided are methods of making and using such antibodies including methods of treating and preventing autoimmune and inflammatory disorders.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: April 23, 2024
    Assignee: Amgen Inc.
    Inventors: Dirk E. Smith, Ian Foltz, Chadwick T. King, Ai Ching Lim, Rutilio Clark, Michael R. Comeau, Randal R. Ketchem, Donghui Shi, Xiaoshan Min, Zhulun Wang
  • Patent number: 11855661
    Abstract: A multiplier is configured to implement multiplication of a first value of M bits and a second value of N bits, and includes P groups of encoders and W layers of inversion compressors. Each group include N encoders and are configured to encode a part of bits in the second value, and a group selection signal and a symbol control input signal corresponding to the each group. The group selection signal and the symbol control input signal are generated based on a part of bits in the first value, and the P groups of encoders perform encoding to obtain P partial products. The W layers of inversion compressors are configured to compress the P partial products.
    Type: Grant
    Filed: May 21, 2022
    Date of Patent: December 26, 2023
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Tuanbao Fan, Yuexing Jiang, Xiaoshan Shi, Rongjun Wang
  • Publication number: 20230015278
    Abstract: A power management system includes a direct current-direct current DC-DC conversion circuit, a first control circuit, a charging circuit, an input port, and an output port. The input port is configured to receive an input voltage. The output port is configured to supply an output voltage to a load. The DC-DC conversion circuit is configured to charge the output port from the input port, to adjust the output voltage. The first control circuit is configured to: obtain a second feedback voltage of the output voltage from the output port, generate a first control signal based on the second feedback voltage and a second reference signal, and supply the first control signal to the charging circuit. The charging circuit charges the output port from the input port based on the first control signal, to supplementally adjust the output voltage.
    Type: Application
    Filed: September 23, 2022
    Publication date: January 19, 2023
    Applicant: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Tuanbao FAN, Ningbo SUN, Xiaoshan SHI, Yi WANG
  • Publication number: 20220374205
    Abstract: A multiplier is configured to implement a binary single-multiplication operation A[m1-1:0]×B[m2-1:0], or an accumulated sum operation of 2N binary multiplications A0[m3-1:0]×B0[m4-1:0]. The multiplier includes P precoders, Q groups of fusion coders, and a compressor. The P precoders and the Q groups of fusion coders are configured to code a first value and a second value in the single-multiplication operation or the multi-multiplication accumulated sum operation, and output a plurality of partial products to the compressor. The compressor may be configured to compress the plurality of partial products corresponding to the single-multiplication operation or the multi-multiplication accumulated sum operation to obtain two accumulated values.
    Type: Application
    Filed: August 2, 2022
    Publication date: November 24, 2022
    Inventors: Tuanbao FAN, Yuexing JIANG, Xiaoshan SHI, Zhao YANG
  • Publication number: 20220294468
    Abstract: A multiplier is configured to implement multiplication of a first value of M bits and a second value of N bits, and includes P groups of encoders and W layers of inversion compressors. Each group include N encoders and are configured to encode a part of bits in the second value, and a group selection signal and a symbol control input signal corresponding to the each group. The group selection signal and the symbol control input signal are generated based on a part of bits in the first value, and the P groups of encoders perform encoding to obtain P partial products. The W layers of inversion compressors are configured to compress the P partial products.
    Type: Application
    Filed: May 21, 2022
    Publication date: September 15, 2022
    Applicant: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Tuanbao Fan, Yuexing Jiang, Xiaoshan Shi, Rongjun Wang
  • Publication number: 20220181890
    Abstract: A charging system includes a voltage conversion circuit, a control circuit, an input end Vin and an output end Vout. The voltage conversion circuit and the control circuit are connected to M batteries, the input end Vin is connected to an external power supply, and the output end Vout is connected to a load. The control circuit is configured to switch a connection relationship between the M batteries, to connect at least one of the M batteries to the voltage conversion circuit, where the connection relationship includes at least one of a serial connection or a parallel connection. The voltage conversion circuit is connected to the input end Vin and the output end Vout; is configured to receive power from the external power supply through the input end Vin, and charge the at least one battery; and is further configured to supply power to the load through the output end Vout.
    Type: Application
    Filed: February 22, 2022
    Publication date: June 9, 2022
    Applicant: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Zhangrong Hu, Xiaoshan Shi