Patents by Inventor Xiaotian Yu
Xiaotian Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12125924Abstract: A method for manufacturing a merged PiN Schottky (MPS) diode may include steps of providing a substrate having a first conductivity type; forming an epitaxial layer with the first conductivity type on top of the substrate; forming a plurality of regions with a second conductivity type under a top surface of the epitaxial layer; forming a plasma spreading layer; depositing and patterning a first Ohmic contact metal on the regions with the second conductivity type; depositing a Schottky contact metal on top of the entire epitaxial layer; and forming a second Ohmic contact metal on a backside of the substrate. In another embodiment, the step of forming a plurality of regions with a second conductivity type may include steps of depositing and patterning a mask layer on the epitaxial layer, implanting P-type dopant into the epitaxial layer, and removing the mask layer.Type: GrantFiled: June 16, 2023Date of Patent: October 22, 2024Inventors: Xiaotian Yu, Zheng Zuo, Ruigang Li
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Publication number: 20230411534Abstract: A method for manufacturing a merged PiN Schottky (MPS) diode may include steps of providing a substrate having a first conductivity type; forming an epitaxial layer with the first conductivity type on top of the substrate; forming a plurality of regions with a second conductivity type under a top surface of the epitaxial layer; forming a plasma spreading layer; depositing and patterning a first Ohmic contact metal on the regions with the second conductivity type; depositing a Schottky contact metal on top of the entire epitaxial layer; and forming a second Ohmic contact metal on a backside of the substrate. In another embodiment, the step of forming a plurality of regions with a second conductivity type may include steps of depositing and patterning a mask layer on the epitaxial layer, implanting P-type dopant into the epitaxial layer, and removing the mask layer.Type: ApplicationFiled: June 16, 2023Publication date: December 21, 2023Applicant: AZ Power, IncInventors: Xiaotian Yu, Zheng Zuo, Ruigang Li
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Patent number: 11728439Abstract: A method for manufacturing a merged PiN Schottky (MPS) diode may include steps of providing a substrate having a first conductivity type; forming an epitaxial layer with the first conductivity type on top of the substrate; forming a plurality of regions with a second conductivity type under a top surface of the epitaxial layer; forming a plasma spreading layer; depositing and patterning a first Ohmic contact metal on the regions with the second conductivity type; depositing a Schottky contact metal on top of the entire epitaxial layer; and forming a second Ohmic contact metal on a backside of the substrate. In another embodiment, the step of forming a plurality of regions with a second conductivity type may include steps of depositing and patterning a mask layer on the epitaxial layer, implanting P-type dopant into the epitaxial layer, and removing the mask layer.Type: GrantFiled: April 20, 2021Date of Patent: August 15, 2023Inventors: Xiaotian Yu, Zheng Zuo, Ruigang Li
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Publication number: 20220181443Abstract: A semiconductor device comprising a substrate having a first conductivity type; an epitaxial layer having the first conductivity type deposited on the substrate; and a MOS structure formed on the epitaxial layer; said MOS structure including multiple well regions with a second conductivity type; multiple source regions with highly doped first conductivity type formed in the well regions; multiple highly doped regions of the second conductivity type formed in the well regions; an insulating gate oxide layer formed on top of the epitaxial layer and spanned adjacent wells and source regions; and a gate electrode formed above the gate oxide layer and spanned adjacent wells and source regions, wherein a JFET region is formed between two adjacent wells; and one or more central implant regions are added with the second conductivity type on a surface of the JFET region to reduce an electric field in the gate oxide.Type: ApplicationFiled: December 8, 2021Publication date: June 9, 2022Applicant: AZ Power, IncInventors: Xiaotian Yu, Zheng Zuo, Ruigang Li
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Publication number: 20210328078Abstract: A method for manufacturing a merged PiN Schottky (MPS) diode may include steps of providing a substrate having a first conductivity type; forming an epitaxial layer with the first conductivity type on top of the substrate; forming a plurality of regions with a second conductivity type under a top surface of the epitaxial layer; forming a plasma spreading layer; depositing and patterning a first Ohmic contact metal on the regions with the second conductivity type; depositing a Schottky contact metal on top of the entire epitaxial layer; and forming a second Ohmic contact metal on a backside of the substrate. In another embodiment, the step of forming a plurality of regions with a second conductivity type may include steps of depositing and patterning a mask layer on the epitaxial layer, implanting P-type dopant into the epitaxial layer, and removing the mask layer.Type: ApplicationFiled: April 20, 2021Publication date: October 21, 2021Applicant: AZ Power, IncInventors: Xiaotian Yu, Zheng Zuo, Ruigang Li
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Publication number: 20210328077Abstract: A semiconductor device may include a substrate having a first conductivity type; an epitaxial layer having the first conductivity type deposited on one side of the substrate; a plurality of regions having a second conductivity type formed under a top surface of the epitaxial layer; a first Ohmic metal patterned and deposited on top of the regions with the second conductivity type; a Schottky contact metal deposited on top of the entire epitaxial layer to form a Schottky junction; and a second Ohmic metal deposited on a backside of the substrate, wherein the regions include one or more wide regions, each having different widths that can be optimized to simultaneously obtain high surge current capability and preserve a low forward voltage drop and reverse leakage current.Type: ApplicationFiled: April 20, 2021Publication date: October 21, 2021Applicant: AZ Power, IncInventors: Xiaotian Yu, Zheng Zuo, Ruigang Li
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Publication number: 20210328076Abstract: A method for manufacturing a merged PiN Schottky (MPS) diode may include steps of providing a substrate having a first conductivity type; forming an epitaxial layer with the first conductivity type on top of the substrate; forming a plurality of regions with a second conductivity type under a top surface of the epitaxial layer; forming a plasma spreading layer; depositing and patterning a first Ohmic contact metal on the regions with the second conductivity type; depositing a Schottky contact metal on top of the entire epitaxial layer; and forming a second Ohmic contact metal on a backside of the substrate. In another embodiment, the step of forming a plurality of regions with a second conductivity type may include steps of depositing and patterning a mask layer on the epitaxial layer, implanting P-type dopant into the epitaxial layer, and removing the mask layer.Type: ApplicationFiled: April 20, 2021Publication date: October 21, 2021Applicant: AZ Power, IncInventors: Xiaotian Yu, Zheng Zuo, Ruigang Li
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Publication number: 20210036167Abstract: A method for manufacturing a merged PiN Schottky (MPS) diode may include steps of providing a substrate having a first conductivity type; forming an epitaxial layer with the first conductivity type on top of the substrate; forming a plurality of regions with a second conductivity type under a top surface of the epitaxial layer; forming a plasma spreading layer; depositing and patterning a first Ohmic contact metal on the regions with the second conductivity type; depositing a Schottky contact metal on top of the entire epitaxial layer; and forming a second Ohmic contact metal on a backside of the substrate. In another embodiment, the step of forming a plurality of regions with a second conductivity type may include steps of depositing and patterning a mask layer on the epitaxial layer, implanting P-type dopant into the epitaxial layer, and removing the mask layer.Type: ApplicationFiled: August 1, 2020Publication date: February 4, 2021Applicant: AZ Power, IncInventors: Xiaotian Yu, Zheng Zuo, Ruigang Li
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Publication number: 20210036165Abstract: In one aspect, a merged PiN Schottky (MPS) diode may include a silicon carbide substrate having a first conductivity type. The epitaxial layer with a first conductivity type was formed on the substrate, which has doping concentration lower than the substrate. A plurality of regions having the second conductivity type different from the first conductivity type are formed under the surface of the epitaxial layer. The Ohmic contact metal is formed on the region of the second conductivity type. The Schottky contact metal is placed on top of the entire epitaxial layer to form a Schottky junction. The Ohmic contact was formed by a cathode electrode on the back side of the substrate.Type: ApplicationFiled: August 1, 2020Publication date: February 4, 2021Applicant: AZ Power, IncInventors: Xiaotian Yu, Zheng Zuo, Ruigang Li
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Publication number: 20210036166Abstract: A method for manufacturing a merged PiN Schottky (MPS) diode may include steps of providing a substrate having a first conductivity type; forming an epitaxial layer with the first conductivity type on top of the substrate; forming a plurality of regions with a second conductivity type under a top surface of the epitaxial layer; depositing and patterning a first Ohmic contact metal on the regions with the second conductivity type; depositing a Schottky contact metal on top of the entire epitaxial layer; and forming a second Ohmic contact metal on a backside of the substrate. In another embodiment, the step of forming a plurality of regions with a second conductivity type under a top surface of the epitaxial layer may include steps of depositing and patterning a mask layer on the epitaxial layer, implanting P-type dopant into the epitaxial layer, and removing the mask layer.Type: ApplicationFiled: August 1, 2020Publication date: February 4, 2021Applicant: AZ Power, IncInventors: Xiaotian Yu, Zheng Zuo, Ruigang Li