Patents by Inventor Xiaotian Zhou

Xiaotian Zhou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240211995
    Abstract: One example system event recommendation includes a processor and at least one memory device. The memory device includes instructions that are executable by the processor to cause the processor to receive a plurality of user features associated with a user, receive a plurality of event features, each of said event features associated with one or more events, and determine a predicted favorite score personalized for each user for each of the one or more events, the predicted favorite score based at least in part on the plurality of user features and the plurality of event features. The memory device also includes instructions that cause the processor to display at least one of the one or more events to the user based at least in part on the personalized predicted favorite score associated with each of the one or more events.
    Type: Application
    Filed: April 14, 2021
    Publication date: June 27, 2024
    Inventors: Chih-Chao Chen, Wan Chen, Wei Dai, Senlin Feng, Haifeng Geng, Tao Huang, Zhibin Mao, Xiaoli Song, Mengxiao Qian, Yang Sun, Melinda Min Xiao-Devins, Qiaojie Yang, Fangyi Zhao, Huilian Zhao, Xiaotian Zhou
  • Patent number: 11488931
    Abstract: Disclosed is a method of manufacturing a semiconductor device that includes securing a lower surface of a wafer to a supporting surface of a carrier substrate formed of copper or other metal having good thermal conductance. Further semiconductor processing for packaging can include forming an RDL on the wafer, etching scribe channels through the wafer, and coating the wafer with encapsulant. After dicing, the metal carrier remains in contact with and supporting the lower surface of the wafer, and the remainder of the wafer remains coated by the encapsulant.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: November 1, 2022
    Assignee: CHENGDU ESWIN SIP TECHNOLOGY CO., LTD.
    Inventors: Minghao Shen, Xiaotian Zhou
  • Patent number: 11274234
    Abstract: Disclosed is an adhesive composition for temporarily bonding a semiconductor workpiece and support carrier pair with improved adhesive film properties. The adhesive composition may include one or more polymer resins, solvents, and a small but critical quantity of surfactants, among others. In operation, the one or more surfactants may improve film continuity, leveling, and reduce voids and defects. Sample semiconductor workpiece includes a semiconductor silicon wafer and sample support carrier includes rigid semiconductor silicon or glass, sapphire or other rigid materials.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: March 15, 2022
    Assignee: CHENGDU ESWIN SIP TECHNOLOGY CO., LTD.
    Inventors: Chunbin Zhang, Xiaotian Zhou, Minghao Shen, Yijiang Hu, Shaolin Zou
  • Patent number: 11177153
    Abstract: Disclosed is a thin subject assisted debonding method for separating temporarily bonded workpiece-carrier pair. The thin subject can be a thin wire, or thin filament, or thin blade. The thin subject can be applied between the workpiece and carrier pair in association with laser debonding or mechanical debonding to provide well controlled and targeted wedging function to the delaminating temporary adhesive and its adjacent substrate to which it is separating from. The workpiece can be a semiconductor wafer that has been thinned and processed, and the carrier can be a semiconductor non-device wafer or any other rigid substrate such as a glass wafer or panel. The application of a thin subject between the workpiece and carrier during debonding provides the advantage of high throughput and low defect rate.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: November 16, 2021
    Assignee: Chengdu ESWIN SiP Technology Co., Ltd.
    Inventors: Chunbin Zhang, Xiaotian Zhou
  • Publication number: 20210287953
    Abstract: Embedded molding fan-out (eMFO) packaging technology has the benefit of delivering six-sided protection of a semiconductor device to reduce delamination failures and provide better reliability and performance. Additionally, semiconductor devices utilizing eMFO packaging technology need not worry about dielectric transition planarity issues, or having to use expensive copper posts or pillars or an extra dielectric layer. In short, implementation of eMFO packaging technology means lower manufacturing cost and better overall performance.
    Type: Application
    Filed: March 12, 2020
    Publication date: September 16, 2021
    Inventors: Minghao Shen, Xiaotian Zhou
  • Publication number: 20210242169
    Abstract: Disclosed is a method of manufacturing a semiconductor device that includes securing a lower surface of a wafer to a supporting surface of a carrier substrate formed of copper or other metal having good thermal conductance. Further semiconductor processing for packaging can include forming an RDL on the wafer, etching scribe channels through the wafer, and coating the wafer with encapsulant. After dicing, the metal carrier remains in contact with and supporting the lower surface of the wafer, and the remainder of the wafer remains coated by the encapsulant.
    Type: Application
    Filed: February 25, 2019
    Publication date: August 5, 2021
    Applicant: CHENGDU ESWIN SIP TECHNOLOGY CO., LTD.
    Inventors: Minghao SHEN, Xiaotian ZHOU
  • Patent number: 10734326
    Abstract: Disclosed is a semiconductor device and method of manufacturing a semiconductor device that includes planarizing surfaces of a semiconductor substrate and a carrier substrate and then placing the semiconductor substrate on the carrier substrate such that the planarized surfaces of each are adjoining and allowing the semiconductor substrate to bond to the carrier substrate using a Van der Waals force. The method also includes forming a metal filled trench around the semiconductor substrate and in contact with the carrier substrate, which can also be formed of metal. The metal filled trench and carrier substrate together form a metal cage-like structure around the semiconductor substrate that can serve as a heat sink, integrated heat spreader, and Electro-Magnetic Interference shield for the semiconductor substrate.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: August 4, 2020
    Assignee: DiDrew Technology (BVI) Limited
    Inventors: Minghao Shen, Xiaotian Zhou, Xiaoming Du, Chunbin Zhang
  • Publication number: 20190295877
    Abstract: Disclosed is a thin subject assisted debonding method for separating temporarily bonded workpiece-carrier pair. The thin subject can be a thin wire, or thin filament, or thin blade. The thin subject can be applied between the workpiece and carrier pair in association with laser debonding or mechanical debonding to provide well controlled and targeted wedging function to the delaminating temporary adhesive and its adjacent substrate to which it is separating from. The workpiece can be a semiconductor wafer that has been thinned and processed, and the carrier can be a semiconductor non-device wafer or any other rigid substrate such as a glass wafer or panel. The application of a thin subject between the workpiece and carrier during debonding provides the advantage of high throughput and low defect rate.
    Type: Application
    Filed: April 27, 2018
    Publication date: September 26, 2019
    Applicant: DiDrew Technology (BVI) Limited
    Inventors: Chunbin Zhang, Xiaotian Zhou
  • Patent number: 10424524
    Abstract: Disclosed is a method of manufacturing a semiconductor device that includes adhering a plurality of semiconductor substrates and a framing member to a supporting surface of a carrier substrate. The semiconductor substrates can be wafers that can be diced or cut into a plurality of dies. Thus, the wafers each have respective active surfaces and at least one respective integrated circuit region. The method can further include encapsulating the framing member and the plurality of semiconductor substrates within an encapsulant. Subsequently, the carrier substrate is removed and a redistribution layer (RDL) is formed on the semiconductor substrates and the framing member.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: September 24, 2019
    Assignees: CHENGDU ESWIN SIP TECHNOLOGY CO., LTD., BEIJING ESWIN TECHNOLOGY CO., LTD.
    Inventors: Minghao Shen, Xiaotian Zhou
  • Publication number: 20190276712
    Abstract: Disclosed is an adhesive composition for temporarily bonding a semiconductor workpiece and support carrier pair with improved adhesive film properties. The adhesive composition may include one or more polymer resins, solvents, and a small but critical quantity of surfactants, among others. In operation, the one or more surfactants may improve film continuity, leveling, and reduce voids and defects. Sample semiconductor workpiece includes a semiconductor silicon wafer and sample support carrier includes rigid semiconductor silicon or glass, sapphire or other rigid materials.
    Type: Application
    Filed: March 8, 2019
    Publication date: September 12, 2019
    Inventors: Chunbin Zhang, Xiaotian Zhou, Minghao Shen, Yijiang Hu, Shaolin Zou
  • Publication number: 20190252324
    Abstract: Disclosed is a semiconductor device and method of manufacturing a semiconductor device that includes planarizing surfaces of a semiconductor substrate and a carrier substrate and then placing the semiconductor substrate on the carrier substrate such that the planarized surfaces of each are adjoining and allowing the semiconductor substrate to bond to the carrier substrate using a Van der Waals force. The method also includes forming a metal filled trench around the semiconductor substrate and in contact with the carrier substrate, which can also be formed of metal. The metal filled trench and carrier substrate together form a metal cage-like structure around the semiconductor substrate that can serve as a heat sink, integrated heat spreader, and Electro-Magnetic Interference shield for the semiconductor substrate.
    Type: Application
    Filed: April 19, 2018
    Publication date: August 15, 2019
    Applicant: DiDrew Technology (BVI) Limited
    Inventors: Minghao Shen, Xiaotian Zhou, Xiaoming Du, Chunbin Zhang
  • Publication number: 20190252278
    Abstract: Disclosed is a method of manufacturing a semiconductor device that includes adhering a plurality of semiconductor substrates and a framing member to a supporting surface of a carrier substrate. The semiconductor substrates can be wafers that can be diced or cut into a plurality of dies. Thus, the wafers each have respective active surfaces and at least one respective integrated circuit region. The method can further include encapsulating the framing member and the plurality of semiconductor substrates within an encapsulant. Subsequently, the carrier substrate is removed and a redistribution layer (RDL) is formed on the semiconductor substrates and the framing member.
    Type: Application
    Filed: March 23, 2018
    Publication date: August 15, 2019
    Applicant: DiDrew Technology (BVI) Limited
    Inventors: Minghao Shen, Xiaotian Zhou
  • Patent number: 10209597
    Abstract: Disclosed is a display module and method of manufacturing the same, where the display module comprises a LCD panel, a driver IC for driving the LCD panel, and a FPC electrically coupled to the driver IC. The LCD panel includes an array of TFT pixels on a TFT array substrate. The TFT array substrate defines a driver cavity and one or more die cavities in which the driver IC and one or more other IC dies are disposed. The driver IC includes an image signal input pad and a driving signal output pad. The driver IC is configured to receive image signals from the FPC, to process the image signals into drive signals, and to transmit the drive signals to TFT pixels via an RDL electrical connection and a through-glass via through the TFT array substrate.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: February 19, 2019
    Assignee: DIDREW TECHNOLOGY (BVI) LIMITED
    Inventors: Minghao Shen, Xiaotian Zhou, Yijiang Hu, Shaolin Zou
  • Patent number: 9940951
    Abstract: A perpendicular magnetic recording (PMR) writer is configured to magnetically record data on a rotatable disk surface. The PMR writer including a pole tip, side shields, an air-bearing surface (ABS) region, a yoke region comprising Silicon Dioxide (SiO2), side gaps and a plurality of throat regions. The side gaps are arranged respectively between the pole tip and the side shields and include SiO2. A side gap width of the plurality of throat regions increases with a side shield throat height above the ABS region for each of the throat regions. The side gap width has a different width variation in each of the throat regions.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: April 10, 2018
    Assignee: Western Digital (Fremont), LLC
    Inventors: Jinqiu Zhang, Feng Liu, Xiaoyu Yang, Ming Jiang, Xiaotian Zhou, Zeyu Ma, Hai Sun
  • Patent number: 9711168
    Abstract: A method provides magnetic write apparatus. A side shield location layer having a location corresponding to the side shield(s) and back and side surfaces is provided. Part of the back surface corresponds to the back surface of the side shield. A nonmagnetic layer adjoining the back and side surface(s) of the side shield location layer is provided. A pole trench is formed in the layers using a first etch process. The nonmagnetic and side shield location layers have an etch selectivity of at least 0.9 and not more than 1.1 for the first etch. A pole is provided in the pole trench. A remaining portion of the side shield location layer is removed using a wet etch. The nonmagnetic layer is nonremovable by the wet etch. Side shield(s) having a back surface substantially the same as the back surface of the side shield location layer are provided.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: July 18, 2017
    Assignee: WESTERN DIGITAL (FREMONT), LLC
    Inventors: Xiaoyu Yang, Jinqiu Zhang, Feng Liu, Xiaotian Zhou, Hai Sun, Ming Jiang
  • Publication number: 20160171992
    Abstract: A process for manufacturing a PMR writer main pole with non-conformal side gaps is provided. The process may include depositing a stitch layer comprising a magnetic material and a second stich layer material over a substrate, forming an air-bearing surface (ABS) region in a first damascene material, and forming a yoke region in a second damascene material. The first damascene material may include Aluminium Oxide (Al2O3). The second damascene material may include Silicon Dioxide (SiO2). Side gap regions may include SiO2.
    Type: Application
    Filed: February 25, 2016
    Publication date: June 16, 2016
    Inventors: JINQIU ZHANG, FENG LIU, XIAOYU YANG, MING JIANG, XIAOTIAN ZHOU, ZEYU MA, HAI SUN
  • Publication number: 20160125899
    Abstract: A writer main pole for a perpendicular magnetic recording system is provided. The writer pole may have a constant sidewall angle from the ABS to yoke and may be formed out of an insulating material and a magnetic material. The sidewall angle of the yoke region may be adjusted during manufacture. The ABS region may correspond to the magnetic material and the yoke region may correspond to the insulating material. The insulating material may comprise Alumina. The magnetic material may comprise a NiFe alloy.
    Type: Application
    Filed: January 13, 2016
    Publication date: May 5, 2016
    Inventors: Jinqiu ZHANG, Hongmei HAN, Feng LIU, Ming JIANG, Xiaotian ZHOU, Zeyu MA
  • Patent number: 9305583
    Abstract: A method provides a magnetic transducer having an air-bearing surface (ABS) location. An intermediate layer that includes a first sublayer in a side shield region and a second sublayer outside of the side shield region is provided. A trench is formed in the intermediate layer using multiple etches. A first etch removes part of the second sublayer, providing a first portion of the trench having a first sidewall angle. A second etch removes part of the first sublayer, providing a second portion of the trench having a second sidewall angle. The second sidewall angle is greater than the first sidewall angle. A main pole is provided in the trench and has a plurality of sidewalls. The sidewalls have the second sidewall angle in the second portion of the trench and at least one main pole sidewall angle corresponding to the first sidewall angle in the first portion of the trench.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: April 5, 2016
    Assignee: Western Digital (Fremont), LLC
    Inventors: Jinqiu Zhang, Feng Liu, Hongmei Han, Ming Sun, Xiaotian Zhou
  • Patent number: 9280990
    Abstract: A method and system provide a magnetic transducer having an air-bearing surface (ABS) location. The method includes forming a trench in the intermediate layer using a plurality of etches. A first etch substantially provides a first portion of the trench having a first sidewall angle. The second etch substantially provides a second portion of the trench having a second sidewall angle. The second sidewall angle is greater than the first sidewall angle. The second portion of the trench includes the ABS location. The method also includes providing a main pole in the trench. The main pole has a plurality of sidewalls. The sidewalls having the first sidewall angle in the first portion of the trench and the second sidewall angle in the second portion of the trench.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: March 8, 2016
    Assignee: Western Digital (Fremont), LLC
    Inventors: Jinqiu Zhang, Feng Liu, Hongmei Han, Ming Sun, Xiaotian Zhou
  • Patent number: 9275657
    Abstract: A process for manufacturing a PMR writer main pole with non-conformal side gaps is provided. The process may include depositing a stitch layer comprising a magnetic material and a second stitch layer material over a substrate, forming an air-bearing surface (ABS) region in a first damascene material, and forming a yoke region in a second damascene material. The first damascene material may include Aluminum Oxide (Al2O3). The second damascene material may include Silicon Dioxide (SiO2). Side gap regions may include SiO2.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: March 1, 2016
    Assignee: Western Digital (Fremont), LLC
    Inventors: Jinqiu Zhang, Feng Liu, Xiaoyu Yang, Ming Jiang, Xiaotian Zhou, Zeyu Ma, Hai Sun