Abstract: The present disclosure provides a display substrate and a display device. The display substrate includes a base substrate and a driving circuit arranged on the base substrate. The driving circuit includes multiple denoising transistors and multiple transistors for driving, and the denoising transistors are electrically connected to a pull-up node. A length of a channel of each of at least a part of the denoising transistors is a first length L1, a length of a channel of each of at least a part of the multiple transistors for driving is a second length L2, and the first length L1 is not equal to the second length L2.

Abstract: Provided are a display substrate and a display device. The first display region includes at least two domains spaced apart in the first direction and a first space between the at least two domains, the second display region includes at least two domains spaced apart in the first direction and a second space located between the at least two domains of the second display region; each pixel units further includes a discharge line and a common electrode strip, the discharge line includes a first conductive part and a second conductive part, the first conductive part is at the first space, the second conductive part is at the second space, the common electrode strip is at an edge of the first display region adjacent to the data lines, and no common electrode strip is arranged on an edge of the second display region adjacent to the data lines.

Abstract: A display panel, including: a substrate including a display region and a non-display region; a second conductive layer including more than one gate line located in the display region, and more than one virtual gate line located in the non-display region; a virtual conductive part, located in the non-display region, where the virtual conductive part is located in a different conductive layer from the virtual gate line, an orthographic projection of the virtual conductive part on the substrate is located within an orthographic projection of the virtual gate line on the substrate, and the virtual conductive part is configured to form an equivalent capacitance with the virtual gate line; and a RC load of the virtual gate line matches with a RC load of the gate line.

Abstract: Provided is an array substrate. The array substrate includes: a base substrate; a plurality of clock lines; a plurality of clock leads; a plurality of shift register units; and a compensation capacitor plate, disposed on the base substrate and in the peripheral region, wherein the compensation capacitor plate is connected to the clock lead, and the compensation capacitor plate and the clock lead are in different layers, an area of the compensation capacitor plate being negatively correlated with a length of the clock lead connected to the compensation capacitor plate.

Abstract: The present disclosure provides a display substrate and a display device. The display substrate includes a base substrate and a driving circuit arranged on the base substrate. The driving circuit includes multiple denoising transistors and multiple transistors for driving, and the denoising transistors are electrically connected to a pull-up node. A length of a channel of each of at least a part of the denoising transistors is a first length L1, a length of a channel of each of at least a part of the multiple transistors for driving is a second length L2, and the first length L1 is not equal to the second length L2.

Abstract: A driving module includes N driving circuits connected in series; the driving circuit includes an input terminal; N is a positive integer; input terminals of first a stages of driving circuits included in the driving module are electrically connected to an initial voltage line; a is a positive integer; an input terminal of an nth stage of driving circuit included in the driving module is electrically connected to an output terminal of an (n?m)th stage of driving circuit included in the driving module through an input cascade line; n and m are positive integers, and m is less than n; the driving module further includes at least one connection line, there is an overlapping portion between an orthographic projection of the connection line on the base substrate and an orthographic projection of the initial voltage line on the base substrate.

Abstract: A display panel includes: a first active area and at least one second active area, a substrate; a plurality of sub-pixels located on the substrate, the plurality of sub-pixels being in the first active area, and each of the sub-pixels including a common electrode; grid lines and data lines, at least one of the data lines being located at a junction of the first active area and the second active area; a plurality of first conductive patterns at least in the second active area, and the first conductive patterns being electrically connected to one of the grid lines or the common electrode; and a plurality of second conductive patterns in the second active area and electrically connected to the data line at the junction, orthographic projections of part first conductive patterns on the substrate overlap orthographic projections of the second conductive patterns on the substrate.

Abstract: The present disclosure provides a display substrate and a display device. The display substrate includes a base substrate and a driving circuit arranged on the base substrate. The driving circuit includes multiple denoising transistors and multiple transistors for driving, and the denoising transistors are electrically connected to a pull-up node. A length of a channel of each of at least a part of the denoising transistors is a first length L1, a length of a channel of each of at least a part of the multiple transistors for driving is a second length L2, and the first length L1 is not equal to the second length L2.

Abstract: The present disclosure relates to the field of display technologies and, in particular to a display panel and an electronic device. The display panel comprises: Q rows of first scanning line groups arranged sequentially along a column direction; M columns of second scanning line groups arranged sequentially along a row direction; and at least one gate drive circuit, located on a side of the Q-th row of the first scanning line groups away from the (Q?1)-th row of the first scanning line groups. Each gate drive circuit comprises Q columns of shift register unit groups cascaded in stages. The q-th stage of the shift register unit groups is connected with the q-th row of the first scanning line groups through at least one column of the second scanning line groups. M?Q>1, 1?q?Q, and M, N, Q, q are all positive integers.

Abstract: A display panel, including: a substrate including a display region and a non-display region; a second conductive layer including more than one gate line located in the display region, and more than one virtual gate line located in the non-display region; a virtual conductive part, located in the non-display region, where the virtual conductive part is located in a different conductive layer from the virtual gate line, an orthographic projection of the virtual conductive part on the substrate is located within an orthographic projection of the virtual gate line on the substrate, and the virtual conductive part is configured to form an equivalent capacitance with the virtual gate line; and a RC load of the virtual gate line matches with a RC load of the gate line.

Abstract: A light control panel, having a dimming area and a peripheral area surrounding the dimming area; wherein the light control panel includes a first substrate and a second substrate oppositely disposed, and a first liquid crystal layer therebetween; the first substrate includes a signal connecting line on the first base substrate; the signal connecting line includes a first signal sub-line and a second signal sub-line which are electrically connected together and in different layers; a connecting position between the first signal sub-line and the second signal sub-line is in the peripheral area; and the slot at a position corresponding to the connecting position between the first signal sub-line and the second signal sub-line is formed with a protrusion, and an orthographic projection of the slot on the first base substrate overlaps an orthographic projection of the first signal sub-line on the first base substrate.

Abstract: A light control panel includes a first substrate and a second substrate oppositely disposed, and a first liquid crystal layer therebetween; the first substrate includes: a first base substrate; and a signal transmission line on a side of the first base substrate close to the first liquid crystal layer and in the peripheral area, the second substrate includes: a second base substrate; and a first black matrix layer on a side of the second base substrate close to the first liquid crystal layer and in the dimming area and the peripheral area; the first black matrix layer has a slot in the peripheral area, and an orthographic projection of at least a part of the slot on the first base substrate is on a side of an orthographic projection of the signal transmission line on the first base substrate, close to the dimming area.

Abstract: Provided is an array substrate. The array substrate includes at least one pad group disposed in a peripheral region of a base substrate, wherein the at least one pad group includes a sector pad group in which the pads are distributed in a sector shape. Therefore, the bonding yield between the array substrate and the circuit board is increased.

Abstract: The present disclosure relates to the field of display technologies and, in particular to a display panel and an electronic device. The display panel comprises: Q rows of first scanning line groups arranged sequentially along a column direction; M columns of second scanning line groups arranged sequentially along a row direction; and at least one gate drive circuit, located on a side of the Q-th row of the first scanning line groups away from the (Q?1)-th row of the first scanning line groups. Each gate drive circuit comprises Q columns of shift register unit groups cascaded in stages. The q-th stage of the shift register unit groups is connected with the q-th row of the first scanning line groups through at least one column of the second scanning line groups. M?Q>1, 1?q?Q, and M, N, Q, q are all positive integers.

Abstract: There is provided a display substrate, including gate lines and data lines, which define pixel units, each pixel unit includes a pixel electrode, at least some pixel units are provided with a conductive bridge line in a same layer as the pixel electrode; in the pixel unit with the conductive bridge line, a first hollow structure is on a first side of a first or second end part of the pixel electrode, an end of the conductive bridge line is in the first hollow structure, a second hollow structure is on a second side of the first end part, an absolute value of a difference between parasitic capacitances respectively formed between the pixel electrode and the data lines on two sides of the pixel electrode and closest thereto is less than or equal to a preset capacitance difference value. A display panel and a display device are further provided.

Abstract: A display panel and a display device are provided. The display panel includes a first substrate and a second substrate arranged oppositely. The first substrate includes a spacer. The second substrate includes: a second base substrate; a data line including, a body portion and a bending portion; and a sub-pixel including a light transmission region. An orthographic projection of the spacer on the second base substrate is adjacent to that of the light transmission region on the second base substrate, the orthographic projection of the spacer on the second base substrate is spaced apart from that of the data line on the second base substrate; an orthographic projection of the bending portion on the second base substrate is bent toward a direction away from the orthographic projection of the spacer on the second base substrate with respect to an orthographic projection of the body portion on the second base substrate.

Abstract: A light control panel includes a first substrate and a second substrate oppositely disposed, and a first liquid crystal layer therebetween; the first substrate includes: a first base substrate; and a signal transmission line on a side of the first base substrate close to the first liquid crystal layer and in the peripheral area, the second substrate includes: a second base substrate; and a first black matrix layer on a side of the second base substrate close to the first liquid crystal layer and in the dimming area and the peripheral area; the first black matrix layer has a slot in the peripheral area, and an orthographic projection of at least a part of the slot on the first base substrate is on a side of an orthographic projection of the signal transmission line on the first base substrate, close to the dimming area.

Abstract: Disclosed is an array substrate, a display panel, and a display apparatus, and belongs to the field of displays.

Abstract: A display panel and a display device are provided. The display panel includes a first substrate and a second substrate arranged oppositely. The first substrate includes a spacer. The second substrate includes: a second base substrate; a data line including, a body portion and a bending portion; and a sub-pixel including a light transmission region. An orthographic projection of the spacer on the second base substrate is adjacent to that of the light transmission region on the second base substrate, the orthographic projection of the spacer on the second base substrate is spaced apart from that of the data line on the second base substrate; an orthographic projection of the bending portion on the second base substrate is bent toward a direction away from the orthographic projection of the spacer on the second base substrate with respect to an orthographic projection of the body portion on the second base substrate.

Abstract: Disclose are a display substrate, a liquid crystal display panel and a display device. The display substrate is provided with a display region. The display substrate includes: a base substrate, and a black matrix arranged on a side of the base substrate. The black matrix includes: a first region corresponding to the display region, and a plurality of frame regions arranged on a periphery of the first region. At least one rectilinear first slit and at least one rectilinear second slit intersecting with the at least one rectilinear first slit are arranged in the at least one of the frame regions, and an extending direction of the at least one rectilinear first slit is same as an extending direction of the at least one of the frame regions.