Abstract: A pixel structure, a display panel and a display device are provided. The pixel structure includes a substrate, and a first pixel, a first TFT and a first gate line that are located on one side of the substrate. The first TFT and the first pixel are connected through a first connection line. The first TFT is electrically connected to the first gate line. The pixel structure also includes: a first compensation structure. The first compensation structure is connected to each of the first TFT and the first pixel. A length direction of the first compensation structure is consistent with a length extension direction of the first gate line. The first compensation structure and the first gate line are arranged in a same layer and are not connected.

Abstract: An array substrate, a driving method and a display device are provided. The array substrate includes a driving module, a plurality of scanning lines, a plurality of data lines and a plurality of pixels. Two scanning lines are arranged between two adjacent rows of subpixels, and two columns of subpixels are arranged between two data lines. In a same row of subpixels, the subpixels electrically coupled to a same data line have at least two colors. In adjacent rows of subpixels, at least two subpixels electrically coupled to a same data line have a same color. The driving module is configured to control, within a display frame, that an overlapping time period and a non-overlapping time period are included between active time periods of the scanning signals provided by at least two scanning lines enabled sequentially.

Abstract: A driving module includes N driving circuits connected in series; the driving circuit includes an input terminal; N is a positive integer; input terminals of first a stages of driving circuits included in the driving module are electrically connected to an initial voltage line; a is a positive integer; an input terminal of an nth stage of driving circuit included in the driving module is electrically connected to an output terminal of an (n?m)th stage of driving circuit included in the driving module through an input cascade line; n and m are positive integers, and m is less than n; the driving module further includes at least one connection line, there is an overlapping portion between an orthographic projection of the connection line on the base substrate and an orthographic projection of the initial voltage line on the base substrate.

Abstract: A light control panel, having a dimming area and a peripheral area surrounding the dimming area; wherein the light control panel includes a first substrate and a second substrate oppositely disposed, and a first liquid crystal layer therebetween; the first substrate includes a signal connecting line on the first base substrate; the signal connecting line includes a first signal sub-line and a second signal sub-line which are electrically connected together and in different layers; a connecting position between the first signal sub-line and the second signal sub-line is in the peripheral area; and the slot at a position corresponding to the connecting position between the first signal sub-line and the second signal sub-line is formed with a protrusion, and an orthographic projection of the slot on the first base substrate overlaps an orthographic projection of the first signal sub-line on the first base substrate.

Abstract: An array substrate and a display apparatus. The array substrate includes: a base substrate including a display region, the display region includes multiple sub-pixel regions arranged in an array, colors of the sub-pixel regions in the same row are the same, at least two adjacent sub-pixel regions in the same column are one pixel region, and colors of the sub-pixel regions in the same one pixel region are different; multiple gate lines at row gaps of the sub-pixel regions, where one gate line is coupled with one row of the sub-pixel regions; multiple data lines at column gaps of the sub-pixel regions; and a barrier wall that is close to the abutment.

Abstract: Provided in the disclosure are an array substrate and a display device. The array substrate includes: a base substrate having a display region; pixel electrode groups arranged in an array in the display region, where each of the pixel electrode groups includes a first pixel electrode and a second pixel electrode, and first pixel electrodes and second pixel electrodes are alternately arranged in a row direction and a column direction separately; data lines passing through column gaps between the pixel electrode groups; connection structures located at row gaps between the pixel electrode groups and connected between the second pixel electrodes and the data lines; common electrode lines passing through column gaps within the pixel electrode groups each; and compensation structures located at the row gaps between the pixel electrode groups and coupled to the first pixel electrodes.

Abstract: Provided are a display substrate and a display device. The first display region includes at least two domains spaced apart in the first direction and a first space between the at least two domains, the second display region includes at least two domains spaced apart in the first direction and a second space located between the at least two domains of the second display region; each pixel units further includes a discharge line and a common electrode strip, the discharge line includes a first conductive part and a second conductive part, the first conductive part is at the first space, the second conductive part is at the second space, the common electrode strip is at an edge of the first display region adjacent to the data lines, and no common electrode strip is arranged on an edge of the second display region adjacent to the data lines.

Abstract: A display substrate, a repair method and a display device are provided. The display substrate includes a base substrate and a driving module arranged on the base substrate; the driving module includes a control switch and a driving circuit; an input terminal of an nth stage of driving circuit included in the driving module is electrically connected to an output terminal of an (n?m)th stage of driving circuit included in the driving module through an input cascade line; n and m are positive integers, and m is less than n; the driving module further includes at least one connection line, the connection line extends along a first direction. The repairing method includes: when previous c stages of driving circuits included in the driving module in the display substrate are cut off, controlling, by the control switch, to connect the connection line and the input cascade line.

Abstract: The present disclosure provides a display substrate and a display device. The display substrate includes a base substrate and a driving circuit arranged on the base substrate. The driving circuit includes multiple denoising transistors and multiple transistors for driving, and the denoising transistors are electrically connected to a pull-up node. A length of a channel of each of at least a part of the denoising transistors is a first length L1, a length of a channel of each of at least a part of the multiple transistors for driving is a second length L2, and the first length L1 is not equal to the second length L2.

Abstract: The present disclosure provides a display substrate and a display device. The display substrate includes a base substrate and a driving circuit arranged on the base substrate. The driving circuit includes multiple denoising transistors and multiple transistors for driving, and the denoising transistors are electrically connected to a pull-up node. A length of a channel of each of at least a part of the denoising transistors is a first length L1, a length of a channel of each of at least a part of the multiple transistors for driving is a second length L2, and the first length L1 is not equal to the second length L2.

Abstract: An array substrate and a display device are provided. An array substrate includes a base substrate, a first data line, a virtual signal line and a driver module, wherein the first data line, the virtual signal line and the driver module are arranged on the base substrate, the driver module includes a multi-stage driving circuit; the multi-stage driving circuit is arranged along the first direction; the driving circuit is used to provide a driving signal; the first data line is arranged between at least two adjacent driving circuits, and the first data line is used to provide a data voltage; the virtual signal line is further arranged between at least two adjacent driving circuits; the virtual signal line is in a floating state. In the embodiments of the present disclosure, the virtual signal line is provided to ensure etching uniformity.

Abstract: A driving module includes N driving circuits connected in series; the driving circuit includes an input terminal; N is a positive integer; input terminals of first a stages of driving circuits included in the driving module are electrically connected to an initial voltage line; a is a positive integer; an input terminal of an nth stage of driving circuit included in the driving module is electrically connected to an output terminal of an (n?m)th stage of driving circuit included in the driving module through an input cascade line; n and m are positive integers, and m is less than n; the driving module further includes at least one connection line, there is an overlapping portion between an orthographic projection of the connection line on the base substrate and an orthographic projection of the initial voltage line on the base substrate.

Abstract: A driving module includes N driving circuits connected in series; the driving circuit includes an input terminal; N is a positive integer; input terminals of first a stages of driving circuits included in the driving module are electrically connected to an initial voltage line; a is a positive integer; an input terminal of an nth stage of driving circuit included in the driving module is electrically connected to an output terminal of an (n?m)th stage of driving circuit included in the driving module through an input cascade line; n and m are positive integers, and m is less than n; the driving module further includes at least one connection line, there is an overlapping portion between an orthographic projection of the connection line on the base substrate and an orthographic projection of the initial voltage line on the base substrate.

Abstract: A display substrate includes a base substrate and a driving module arranged on the base substrate; the driving module includes a control switch and a driving circuit; an input terminal of an nth stage of driving circuit included in the driving module is electrically connected to an output terminal of an (n?m)th stage of driving circuit included in the driving module through an input cascade line; n and m are positive integers, and m is less than n; the driving module further includes at least one connection line, the connection line extends along a first direction; there is an overlapping area between an orthographic projection of the connection line on the base substrate and an orthographic projection of the start voltage line and/or the input cascade line on the base substrate; the control switch is electrically connected to the connection line.

Abstract: The present disclosure provides a display substrate and a display device. The display substrate includes a base substrate and a driving circuit arranged on the base substrate. The driving circuit includes multiple denoising transistors and multiple transistors for driving, and the denoising transistors are electrically connected to a pull-up node. A length of a channel of each of at least a part of the denoising transistors is a first length L1, a length of a channel of each of at least a part of the multiple transistors for driving is a second length L2, and the first length L1 is not equal to the second length L2.

Abstract: Provided are a display substrate and a display device. The first display region includes at least two domains spaced apart in the first direction and a first space between the at least two domains, the second display region includes at least two domains spaced apart in the first direction and a second space located between the at least two domains of the second display region; each pixel units further includes a discharge line and a common electrode strip, the discharge line includes a first conductive part and a second conductive part, the first conductive part is at the first space, the second conductive part is at the second space, the common electrode strip is at an edge of the first display region adjacent to the data lines, and no common electrode strip is arranged on an edge of the second display region adjacent to the data lines.

Abstract: A display panel, including: a substrate including a display region and a non-display region; a second conductive layer including more than one gate line located in the display region, and more than one virtual gate line located in the non-display region; a virtual conductive part, located in the non-display region, where the virtual conductive part is located in a different conductive layer from the virtual gate line, an orthographic projection of the virtual conductive part on the substrate is located within an orthographic projection of the virtual gate line on the substrate, and the virtual conductive part is configured to form an equivalent capacitance with the virtual gate line; and a RC load of the virtual gate line matches with a RC load of the gate line.

Abstract: Provided is an array substrate. The array substrate includes: a base substrate; a plurality of clock lines; a plurality of clock leads; a plurality of shift register units; and a compensation capacitor plate, disposed on the base substrate and in the peripheral region, wherein the compensation capacitor plate is connected to the clock lead, and the compensation capacitor plate and the clock lead are in different layers, an area of the compensation capacitor plate being negatively correlated with a length of the clock lead connected to the compensation capacitor plate.

Abstract: The present disclosure provides a display substrate and a display device. The display substrate includes a base substrate and a driving circuit arranged on the base substrate. The driving circuit includes multiple denoising transistors and multiple transistors for driving, and the denoising transistors are electrically connected to a pull-up node. A length of a channel of each of at least a part of the denoising transistors is a first length L1, a length of a channel of each of at least a part of the multiple transistors for driving is a second length L2, and the first length L1 is not equal to the second length L2.

Abstract: A driving module includes N driving circuits connected in series; the driving circuit includes an input terminal; N is a positive integer; input terminals of first a stages of driving circuits included in the driving module are electrically connected to an initial voltage line; a is a positive integer; an input terminal of an nth stage of driving circuit included in the driving module is electrically connected to an output terminal of an (n?m)th stage of driving circuit included in the driving module through an input cascade line; n and m are positive integers, and m is less than n; the driving module further includes at least one connection line, there is an overlapping portion between an orthographic projection of the connection line on the base substrate and an orthographic projection of the initial voltage line on the base substrate.