Abstract: An array substrate and a display apparatus. The array substrate includes: a base substrate including a display region, the display region includes multiple sub-pixel regions arranged in an array, colors of the sub-pixel regions in the same row are the same, at least two adjacent sub-pixel regions in the same column are one pixel region, and colors of the sub-pixel regions in the same one pixel region are different; multiple gate lines at row gaps of the sub-pixel regions, where one gate line is coupled with one row of the sub-pixel regions; multiple data lines at column gaps of the sub-pixel regions; and a barrier wall that is close to the abutment.

Abstract: Provided in the disclosure are an array substrate and a display device. The array substrate includes: a base substrate having a display region; pixel electrode groups arranged in an array in the display region, where each of the pixel electrode groups includes a first pixel electrode and a second pixel electrode, and first pixel electrodes and second pixel electrodes are alternately arranged in a row direction and a column direction separately; data lines passing through column gaps between the pixel electrode groups; connection structures located at row gaps between the pixel electrode groups and connected between the second pixel electrodes and the data lines; common electrode lines passing through column gaps within the pixel electrode groups each; and compensation structures located at the row gaps between the pixel electrode groups and coupled to the first pixel electrodes.

Abstract: Provided are a display substrate and a display device. The first display region includes at least two domains spaced apart in the first direction and a first space between the at least two domains, the second display region includes at least two domains spaced apart in the first direction and a second space located between the at least two domains of the second display region; each pixel units further includes a discharge line and a common electrode strip, the discharge line includes a first conductive part and a second conductive part, the first conductive part is at the first space, the second conductive part is at the second space, the common electrode strip is at an edge of the first display region adjacent to the data lines, and no common electrode strip is arranged on an edge of the second display region adjacent to the data lines.

Abstract: A display substrate, a repair method and a display device are provided. The display substrate includes a base substrate and a driving module arranged on the base substrate; the driving module includes a control switch and a driving circuit; an input terminal of an nth stage of driving circuit included in the driving module is electrically connected to an output terminal of an (n?m)th stage of driving circuit included in the driving module through an input cascade line; n and m are positive integers, and m is less than n; the driving module further includes at least one connection line, the connection line extends along a first direction. The repairing method includes: when previous c stages of driving circuits included in the driving module in the display substrate are cut off, controlling, by the control switch, to connect the connection line and the input cascade line.

Abstract: The present disclosure provides a display substrate and a display device. The display substrate includes a base substrate and a driving circuit arranged on the base substrate. The driving circuit includes multiple denoising transistors and multiple transistors for driving, and the denoising transistors are electrically connected to a pull-up node. A length of a channel of each of at least a part of the denoising transistors is a first length L1, a length of a channel of each of at least a part of the multiple transistors for driving is a second length L2, and the first length L1 is not equal to the second length L2.

Abstract: The present disclosure provides a display substrate and a display device. The display substrate includes a base substrate and a driving circuit arranged on the base substrate. The driving circuit includes multiple denoising transistors and multiple transistors for driving, and the denoising transistors are electrically connected to a pull-up node. A length of a channel of each of at least a part of the denoising transistors is a first length L1, a length of a channel of each of at least a part of the multiple transistors for driving is a second length L2, and the first length L1 is not equal to the second length L2.

Abstract: An array substrate and a display device are provided. An array substrate includes a base substrate, a first data line, a virtual signal line and a driver module, wherein the first data line, the virtual signal line and the driver module are arranged on the base substrate, the driver module includes a multi-stage driving circuit; the multi-stage driving circuit is arranged along the first direction; the driving circuit is used to provide a driving signal; the first data line is arranged between at least two adjacent driving circuits, and the first data line is used to provide a data voltage; the virtual signal line is further arranged between at least two adjacent driving circuits; the virtual signal line is in a floating state. In the embodiments of the present disclosure, the virtual signal line is provided to ensure etching uniformity.

Abstract: A driving module includes N driving circuits connected in series; the driving circuit includes an input terminal; N is a positive integer; input terminals of first a stages of driving circuits included in the driving module are electrically connected to an initial voltage line; a is a positive integer; an input terminal of an nth stage of driving circuit included in the driving module is electrically connected to an output terminal of an (n?m)th stage of driving circuit included in the driving module through an input cascade line; n and m are positive integers, and m is less than n; the driving module further includes at least one connection line, there is an overlapping portion between an orthographic projection of the connection line on the base substrate and an orthographic projection of the initial voltage line on the base substrate.

Abstract: A driving module includes N driving circuits connected in series; the driving circuit includes an input terminal; N is a positive integer; input terminals of first a stages of driving circuits included in the driving module are electrically connected to an initial voltage line; a is a positive integer; an input terminal of an nth stage of driving circuit included in the driving module is electrically connected to an output terminal of an (n?m)th stage of driving circuit included in the driving module through an input cascade line; n and m are positive integers, and m is less than n; the driving module further includes at least one connection line, there is an overlapping portion between an orthographic projection of the connection line on the base substrate and an orthographic projection of the initial voltage line on the base substrate.

Abstract: A display substrate includes a base substrate and a driving module arranged on the base substrate; the driving module includes a control switch and a driving circuit; an input terminal of an nth stage of driving circuit included in the driving module is electrically connected to an output terminal of an (n?m)th stage of driving circuit included in the driving module through an input cascade line; n and m are positive integers, and m is less than n; the driving module further includes at least one connection line, the connection line extends along a first direction; there is an overlapping area between an orthographic projection of the connection line on the base substrate and an orthographic projection of the start voltage line and/or the input cascade line on the base substrate; the control switch is electrically connected to the connection line.

Abstract: The present disclosure provides a display substrate and a display device. The display substrate includes a base substrate and a driving circuit arranged on the base substrate. The driving circuit includes multiple denoising transistors and multiple transistors for driving, and the denoising transistors are electrically connected to a pull-up node. A length of a channel of each of at least a part of the denoising transistors is a first length L1, a length of a channel of each of at least a part of the multiple transistors for driving is a second length L2, and the first length L1 is not equal to the second length L2.

Abstract: Provided are a display substrate and a display device. The first display region includes at least two domains spaced apart in the first direction and a first space between the at least two domains, the second display region includes at least two domains spaced apart in the first direction and a second space located between the at least two domains of the second display region; each pixel units further includes a discharge line and a common electrode strip, the discharge line includes a first conductive part and a second conductive part, the first conductive part is at the first space, the second conductive part is at the second space, the common electrode strip is at an edge of the first display region adjacent to the data lines, and no common electrode strip is arranged on an edge of the second display region adjacent to the data lines.

Abstract: A display panel, including: a substrate including a display region and a non-display region; a second conductive layer including more than one gate line located in the display region, and more than one virtual gate line located in the non-display region; a virtual conductive part, located in the non-display region, where the virtual conductive part is located in a different conductive layer from the virtual gate line, an orthographic projection of the virtual conductive part on the substrate is located within an orthographic projection of the virtual gate line on the substrate, and the virtual conductive part is configured to form an equivalent capacitance with the virtual gate line; and a RC load of the virtual gate line matches with a RC load of the gate line.

Abstract: Provided is an array substrate. The array substrate includes: a base substrate; a plurality of clock lines; a plurality of clock leads; a plurality of shift register units; and a compensation capacitor plate, disposed on the base substrate and in the peripheral region, wherein the compensation capacitor plate is connected to the clock lead, and the compensation capacitor plate and the clock lead are in different layers, an area of the compensation capacitor plate being negatively correlated with a length of the clock lead connected to the compensation capacitor plate.

Abstract: The present disclosure provides a display substrate and a display device. The display substrate includes a base substrate and a driving circuit arranged on the base substrate. The driving circuit includes multiple denoising transistors and multiple transistors for driving, and the denoising transistors are electrically connected to a pull-up node. A length of a channel of each of at least a part of the denoising transistors is a first length L1, a length of a channel of each of at least a part of the multiple transistors for driving is a second length L2, and the first length L1 is not equal to the second length L2.

Abstract: A driving module includes N driving circuits connected in series; the driving circuit includes an input terminal; N is a positive integer; input terminals of first a stages of driving circuits included in the driving module are electrically connected to an initial voltage line; a is a positive integer; an input terminal of an nth stage of driving circuit included in the driving module is electrically connected to an output terminal of an (n?m)th stage of driving circuit included in the driving module through an input cascade line; n and m are positive integers, and m is less than n; the driving module further includes at least one connection line, there is an overlapping portion between an orthographic projection of the connection line on the base substrate and an orthographic projection of the initial voltage line on the base substrate.

Abstract: A display panel includes: a first active area and at least one second active area, a substrate; a plurality of sub-pixels located on the substrate, the plurality of sub-pixels being in the first active area, and each of the sub-pixels including a common electrode; grid lines and data lines, at least one of the data lines being located at a junction of the first active area and the second active area; a plurality of first conductive patterns at least in the second active area, and the first conductive patterns being electrically connected to one of the grid lines or the common electrode; and a plurality of second conductive patterns in the second active area and electrically connected to the data line at the junction, orthographic projections of part first conductive patterns on the substrate overlap orthographic projections of the second conductive patterns on the substrate.

Abstract: The present disclosure provides a display substrate and a display device. The display substrate includes a base substrate and a driving circuit arranged on the base substrate. The driving circuit includes multiple denoising transistors and multiple transistors for driving, and the denoising transistors are electrically connected to a pull-up node. A length of a channel of each of at least a part of the denoising transistors is a first length L1, a length of a channel of each of at least a part of the multiple transistors for driving is a second length L2, and the first length L1 is not equal to the second length L2.

Abstract: The present disclosure relates to the field of display technologies and, in particular to a display panel and an electronic device. The display panel comprises: Q rows of first scanning line groups arranged sequentially along a column direction; M columns of second scanning line groups arranged sequentially along a row direction; and at least one gate drive circuit, located on a side of the Q-th row of the first scanning line groups away from the (Q?1)-th row of the first scanning line groups. Each gate drive circuit comprises Q columns of shift register unit groups cascaded in stages. The q-th stage of the shift register unit groups is connected with the q-th row of the first scanning line groups through at least one column of the second scanning line groups. M?Q>1, 1?q?Q, and M, N, Q, q are all positive integers.

Abstract: A display panel, including: a substrate including a display region and a non-display region; a second conductive layer including more than one gate line located in the display region, and more than one virtual gate line located in the non-display region; a virtual conductive part, located in the non-display region, where the virtual conductive part is located in a different conductive layer from the virtual gate line, an orthographic projection of the virtual conductive part on the substrate is located within an orthographic projection of the virtual gate line on the substrate, and the virtual conductive part is configured to form an equivalent capacitance with the virtual gate line; and a RC load of the virtual gate line matches with a RC load of the gate line.