Abstract: The present disclosure discloses a method for determining fidelity of a qubit gate in a quantum processor, and a storage medium. The method includes: determining environmental qubit gates associated with a two-qubit gate in the quantum processor, where the two-qubit gate interacts with the environmental qubit gates in the quantum processor; determining a fidelity error of the environmental qubit gates based on a fidelity error of the two-qubit gate; determining frequency of the environmental qubit gates based on the fidelity error of the environmental qubit gates; and determining fidelity of the two-qubit gate based on the frequency of the environmental qubit gates. The present disclosure solves the technical problem of being unable to determine the fidelity of the two-qubit gate.

Abstract: This disclosure discloses a method for determining fidelity of a qubit gate in a quantum chip, and a storage medium. The method includes: determining environmental qubit gates associated with a two-qubit gate in the quantum chip, where the two-qubit gate interacts with the environmental qubit gates in the quantum chip; determining, based on the two-qubit gate and the environmental qubit gates, a first target matrix and a corresponding first evolution matrix, where the first target matrix is a diagonal matrix constructed based on a logic gate, and the first evolution matrix is a matrix obtained after time-dependent evolution; and determining the fidelity of the two-qubit gate based on the number of the environmental qubit gates associated with the two-qubit gate, the first target matrix, and the first evolution matrix. This disclosure solves the technical problem of being unable to determine the fidelity of the two-qubit gate.

Abstract: A quantum layout optimization method includes: determining target Hamiltonian parameters of a quantum device; determining an initial quantum layout of the quantum device and initial geometric parameters of the initial quantum layout; determining a target gradient of Hamiltonian parameters of the quantum device to geometric parameters of the initial quantum layout; and adjusting the initial geometric parameters based on the target gradient to have the Hamiltonian parameters of the quantum device be the target Hamiltonian parameters to obtain a target quantum layout.

Abstract: A parameter calibration method is provided. The parameter calibration method includes: obtaining a control parameter to be calibrated; determining a simulation running error corresponding to a quantum chip; determining calibration data corresponding to the control parameter to be calibrated based on the simulation running error; and obtaining a calibrated control parameter by calibrating the control parameter to be calibrated based on the calibration data, wherein the calibrated control parameter is used for controlling operation of the quantum chip.

Abstract: A parameter calibration method is provided. The parameter calibration method includes: obtaining a control parameter to be calibrated; determining a simulation running error corresponding to a quantum chip; determining calibration data corresponding to the control parameter to be calibrated based on the simulation running error; and obtaining a calibrated control parameter by calibrating the control parameter to be calibrated based on the calibration data, wherein the calibrated control parameter is used for controlling operation of the quantum chip.

Abstract: Methods, apparatuses, and systems include: obtaining a quantum gate precision corresponding to a quantum chip; performing a reverse differentiation operation on the quantum gate precision to obtain a gradient of a chip parameter and a gradient of a control parameter, wherein the chip parameter and the control parameter are configured to control the quantum chip to perform operations, updating the chip parameter based on the gradient of the chip parameter, and updating the control parameter based on the gradient of the control parameter.