Abstract: An information handling system includes a memory and a processor. The memory stores an automation test set for the information handling system, and the automation test set includes multiple test cases. The processor determines that each test case of a subset of the test cases includes a same common and time-intensive test step (CTITS). The processor creates a CTITS module based on the same CTITS in the subset test cases. The processor also creates multiple normal test cases based on the test cases of the automation test set. The processor creates a virtual test case to implement the CTITS, executes first test step code within a first normal test case, and executes second test step code within a second normal test case. In response to execution of both the first and second test step code being completed, the processor executes the CTITS via the CTITS module.

Abstract: An information handling system determines a first function identifier associated with an error message, determines a second function identifier associated with the first function identifier, and sets a center parameter value and a width parameter value that are used to calculate a movable range that includes the first function identifier and the second function identifier.

Abstract: Virtual cable modem termination system redundancy may be provided. First, a new virtual cable modem termination system (vCMTS) instance may be spawned. Then a backhaul connection between the new vCMTS instance and a data center network may be created. Next, a database connection between the new vCMTS instance and a database may be created. Upstream and downstream traffic of a node may then be switched from an active vCMTS instance to the new vCMTS instance.

Abstract: Virtual cable modem termination system redundancy may be provided. First, a new virtual cable modem termination system (vCMTS) instance may be spawned. Then a backhaul connection between the new vCMTS instance and a data center network may be created. Next, a database connection between the new vCMTS instance and a database may be created. Upstream and downstream traffic of a node may then be switched from an active vCMTS instance to the new vCMTS instance.

Abstract: Processes for masking electronic devices, including, but not limited to, electronic subassemblies, prior to the application of protective coatings to the electronic devices are disclosed. Such processes include the use of a plurality of different masking techniques in combination to mask the electronic device. Different masking techniques may be used to mask different features and/or components of the electronic device. Some features and/or components may be masked by way of two or more masking techniques. With one or more masks in place, an electronic device may be protectively coated. After a protective coating has been applied to the electronic device, at least a portion of the mask(s) may be removed from the electronic device. Protectively coated electronic devices may then be assembled with one another.

Abstract: Processes for masking electronic devices, including, but not limited to, electronic subassemblies, prior to the application of protective coatings to the electronic devices are disclosed. Such processes include the use of a plurality of different masking techniques in combination to mask the electronic device. Different masking techniques may be used to mask different features and/or components of the electronic device. Some features and/or components may be masked by way of two or more masking techniques. With one or more masks in place, an electronic device may be protectively coated. After a protective coating has been applied to the electronic device, at least a portion of the mask(s) may be removed from the electronic device. Protectively coated electronic devices may then be assembled with one another.

Abstract: An atomic transaction includes one or more memory access operations that are completed atomically. A Best-Effort Transaction (BET) system makes its best effort to complete each atomic transaction without guaranteeing completion of all atomic transactions. When an atomic transaction is aborted, BET may provide software with appropriate runtime information such as cause of the abortion. With proper coherence layer enhancements, BET can be implemented efficiently for multiprocessor systems, using caches as buffers for data accessed by atomic transactions. Furthermore, with appropriate fairness support, forward progress can be guaranteed for atomic transactions that incur no buffer overflow.

Abstract: A system includes a deterministic system, and a controller electrically coupled to the deterministic system via a link, wherein the controller comprises a transaction scheduling mechanism that allows data responses from the deterministic system, corresponding to requests issued from the controller, to be returned out of order.

Abstract: The present invention broadly contemplates braids and fibers, high-level programming constructs which facilitate the creation of programs that are partially ordered, to address the continuing trend of ever-increasing processor speeds and attendant increases in memory latencies. These partial orders can be used to respond adaptively to memory latencies. It is shown how these constructs can be effectively supported with simple and inexpensive instruction set and micro-architectural extensions.

Abstract: Color-based caching allows each cache line to be distinguished by a specific color, and enables the manipulation of cache behavior based upon the colors of the cache lines. When multiple threads are able to share a cache, effective cache management is critical to overall performance. Color-based caching provides an effective method to better utilize caches and avoid unnecessary cache thrashing and pollution. Hardware maintains color-based counters relative to the cache lines to monitor and obtain feedback on cache line events. These counters are utilized for cache coherence transactions in multiple processor systems.

Abstract: A computer-implemented method for memory access monitoring, implemented by a managed runtime environment computer system including a controller that monitors application behavior and determines actions to be taken to change a behavior of an application, and a runtime, dynamic compiler that analyzes the application and generates code sequences to access a memory access monitoring (MAM) mechanism, includes determining monitor information of a plurality of fields of a memory block to drive an optimization of the application.

Abstract: Memory Access Coloring provides architecture support that allows software to classify memory accesses into different congruence classes by specifying a color for each memory access operation. The color information is received and recorded by the underlying system with appropriate granularity. This allows hardware to monitor color-based cache monitoring information and provide such feedback to the software to enable various runtime optimizations. It also enables enforcement of different memory consistency models for memory regions with different colors at the same time.

Abstract: Systems and methods for cache replacement monitoring (CRM) are provided. The system includes a monitored cache comprising a monitored cache line set, the monitored cache line set comprising at least one cache line capable of holding data of a monitored address; and a CRM mechanism operatively associated with the monitored cache. The CRM mechanism collects CRM information for the monitored address. The method includes the steps of collecting CRM information for a monitored address in a monitored cache; and recording the CRM information for the monitored address, when at least one of (1) the monitored address is cached in the monitored cache, (2) the monitored address is replaced in the monitored cache, (3) any cache line in a cache line set corresponding to the monitored address is cached in the monitored cache, and (4) any cache line in a cache line set corresponding to the monitored address is replaced in the monitored cache.

Abstract: A method for performing a transaction including a transaction head and a transaction tail, includes executing the transaction head, including executing at least one memory reserve instruction to reserve a transactional memory location that are accessed in the transaction and executing the transaction tail, wherein the transaction cannot be aborted due to a data race on that transactional memory location while executing the transaction tail, wherein data of memory write operations to the transactional memory location is committed without being buffered.

Abstract: There is disclosed a method and apparatus for handling transaction buffer overflow in a multi-processor system as well as a transaction memory system in a multi-processor system. The method comprises the steps of: when overflow occurs in a transaction buffer of one processor, disabling peer processors from entering transactions, and waiting for any processor having a current transaction to complete its current transaction; re-executing the transaction resulting in the transaction buffer overflow without using the transaction buffer; and when the transaction execution is completed, enabling the peer processors for entering transactions.

Abstract: A method for reconfiguring a cache memory is provided. The method in one aspect may include analyzing one or more characteristics of an execution entity accessing a cache memory and reconfiguring the cache based on the one or more characteristics analyzed. Examples of analyzed characteristic may include but are not limited to data structure used by the execution entity, expected reference pattern of the execution entity, type of an execution entity, heat and power consumption of an execution entity, etc. Examples of cache attributes that may be reconfigured may include but are not limited to associativity of the cache memory, amount of the cache memory available to store data, coherence granularity of the cache memory, line size of the cache memory, etc.

Abstract: In a computer system with a memory hierarchy, when a high-level cache supplies a data copy to a low-level cache, the shared copy can be either volatile or non-volatile. When the data copy is later replaced from the low-level cache, if the data copy is non-volatile, it needs to be written back to the high-level cache; otherwise it can be simply flushed from the low-level cache. The high-level cache can employ a volatile-prediction mechanism that adaptively determines whether a volatile copy or a non-volatile copy should be supplied when the high-level cache needs to send data to the low-level cache. An exemplary volatile-prediction mechanism suggests use of a non-volatile copy if the cache line has been accessed consecutively by the low-level cache. Further, the low-level cache can employ a volatile-promotion mechanism that adaptively changes a data copy from volatile to non-volatile according to some promotion policy, or changes a data copy from non-volatile to volatile according to some demotion policy.

Abstract: A system, method, and computer readable article of manufacture for sharing buffer management. The system includes: a predictor module to predict at runtime a transaction data size of a transaction according to history information of the transaction; and a resource management module to allocate sharing buffer resources for the transaction according to the predicted transaction data size in response to beginning of the transaction, to record an actual sharing buffer size occupied by the transaction in response to the successful commitment of the transaction, and to update the history information of the transaction.

Abstract: A computer readable medium is provided embodying instructions executable by a processor to perform a method for performing a transaction including a transaction head and a transaction tail, the method includes executing the transaction head, including executing at least one memory reserve instruction to reserve a transactional memory location that are accessed in the transaction and executing the transaction tail, wherein the transaction cannot be aborted due to a data race on that transactional memory location while executing the transaction tail, wherein data of memory write operations to the transactional memory location is committed without being buffered.

Abstract: A method for performing a transaction including a transaction head and a transaction tail, includes executing the transaction head, including executing at least one memory reserve instruction to reserve a transactional memory location that are accessed in the transaction and executing the transaction tail, wherein the transaction cannot be aborted due to a data race on that transactional memory location while executing the transaction tail, wherein data of memory write operations to the transactional memory location is committed without being buffered.