Patents by Inventor Xiaowei Yao

Xiaowei Yao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240272142
    Abstract: Provided is a method for determining whitening efficacy of a cosmetic raw material. In the disclosure, specific binding of melanocyte-stimulating hormone (?-MSH) to melanocortical receptor I (MC1R) on melanocytes activates adenylyl cyclase (AC). The AC could catalyze the conversion of adenosine triphosphate (ATP) into cyclic adenosine monophosphate (cAMP), causing an increased level of intracellular cAMP. Increased CAMP level activates tyrosinase through protein kinase A (PKA), thereby promoting melanin production, and then achieving the determination of a relative melanin content.
    Type: Application
    Filed: January 25, 2024
    Publication date: August 15, 2024
    Inventors: Meirong Qin, Xiaowei Wang, Xiaoyu Feng, Zhihong Yao, Ping Wang, Pei Lin, Zhanlin Ma, Xiaoqiong Zheng
  • Patent number: 9892541
    Abstract: A method for a programmable primitive setup in a 3D graphics pipeline is introduced to contain at least the following steps. Information about first and third primitives is obtained from a buffer. The information about all or a portion of the first primitives is packed and sent to an SS (Setup Shader) thread. Information about a second primitive to be clipped is packed and sent to a GBS (Guard-Band-clipping Shader) thread. The information about all or a portion of the third primitives is packed and sent to an AS (Attribute Shader) thread.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: February 13, 2018
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventors: Huaisheng Zhang, Zhou Hong, Xiaowei Yao
  • Publication number: 20170053429
    Abstract: A method for a programmable primitive setup in a 3D graphics pipeline is introduced to contain at least the following steps. Information about first and third primitives is obtained from a buffer. The information about all or a portion of the first primitives is packed and sent to an SS (Setup Shader) thread. Information about a second primitive to be clipped is packed and sent to a GBS (Guard-Band-clipping Shader) thread. The information about all or a portion of the third primitives is packed and sent to an AS (Attribute Shader) thread.
    Type: Application
    Filed: October 22, 2015
    Publication date: February 23, 2017
    Inventors: Huaisheng ZHANG, Zhou HONG, Xiaowei YAO
  • Patent number: 7405155
    Abstract: A circuit package includes a substrate having an opening and a single unitary heat sink adapted to effectively dissipate heat is positioned in the opening to expose top and bottom surfaces which are respectively coplanar with top and bottom surfaces of the substrate. Selective plating includes applying first and second metal patterns to a substrate surface, creating a potential voltage difference between the first metal pattern and a metal source, and plating the first metal pattern by attracting a first metal type to the voltage potential of the first metal pattern. The voltage potential of the first metal pattern is less than the voltage potential of the metal source.
    Type: Grant
    Filed: January 18, 2006
    Date of Patent: July 29, 2008
    Assignee: Intel Corporation
    Inventors: Xiaowei Yao, Tam Nguyen, Marc Finot, Rickie C. Lake, Jeffrey A. Bennett, Robert Kohler
  • Patent number: 7350987
    Abstract: Optoelectronic packages with one or more feed-throughs having a cutout allow optical fibers that have been coupled to a component (e.g., an optical component, an electrical component, a structural component) to be fed through more easily than a package having feed-throughs without a cutout. In one embodiment, the cut in the feed-through is on the opposite side of the initial direction of the threading. That is, if the fiber is to come from above the feed-through, the cut is placed on the bottom of the feed-through. The placement of the cut on the feed-through allows a fiber previously attached to a component to be fed through without excessive curvature of the fiber.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: April 1, 2008
    Assignee: Intel Corporation
    Inventors: Marc A. Finot, Xiaowei Yao
  • Publication number: 20060221427
    Abstract: Impedance matching circuits for optical transmitters are disclosed. In one aspect, an impedance matching circuit may include an equalizer circuit, a resistor coupled between the equalizer circuit and ground, and an electro-absorption modulator or other light intensity modulator coupled in series with the equalizer circuit and coupled in parallel with the resistor. In a further aspect, the equalizer circuit may have an impedance that varies with frequency and may include an inductor, and a second resistor that is coupled in parallel with the inductor. Methods of making and using the impedance matching circuits are also disclosed. Optical transmitters, transceivers, and other systems including the impedance matching circuits are also disclosed.
    Type: Application
    Filed: March 31, 2005
    Publication date: October 5, 2006
    Inventors: Xin Wu, Xiaowei Yao
  • Publication number: 20060121732
    Abstract: A circuit package includes a substrate having an opening and a single unitary heat sink adapted to effectively dissipate heat is positioned in the opening to expose top and bottom surfaces which are respectively coplanar with top and bottom surfaces of the substrate. Selective plating includes applying first and second metal patterns to a substrate surface, creating a potential voltage difference between the first metal pattern and a metal source, and plating the first metal pattern by attracting a first metal type to the voltage potential of the first metal pattern. The voltage potential of the first metal pattern is less than the voltage potential of the metal source.
    Type: Application
    Filed: January 18, 2006
    Publication date: June 8, 2006
    Inventors: Xiaowei Yao, Tam Nguyen, Marc Finot, Rickie Lake, Jeffrey Bennett, Robert Kohler
  • Patent number: 7019394
    Abstract: A circuit package includes a base portion and a first metal pattern disposed on a substrate surface. Second and third metal patterns are disposed on another substrate surface, and electrically coupled to first and second vias. The third metal pattern forms a gap to electrically isolate it from the second metal pattern. A circuit package includes a substrate having an opening and a single heat sink positioned in the opening to expose top and bottom surfaces through top and bottom surfaces of the substrate. Selective plating includes applying first and second metal patterns to a substrate surface, creating a potential voltage difference between the first metal pattern and a metal source, and plating the first metal pattern by attracting a first metal type to the voltage potential of the first metal pattern. The voltage potential of the first metal pattern is less than the voltage potential of the metal source.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: March 28, 2006
    Assignee: Intel Corporation
    Inventors: Xiaowei Yao, Tam Nguyen, Marc Finot, Rickie C. Lake, Jeffrey A. Bennett, Robert Kohler
  • Publication number: 20050077609
    Abstract: A circuit package includes a base portion and a first metal pattern disposed on a substrate surface. Second and third metal patterns are disposed on another substrate surface, and electrically coupled to first and second vias. The third metal pattern forms a gap to electrically isolate it from the second metal pattern. A circuit package includes a substrate having an opening and a single heat sink positioned in the opening to expose top and bottom surfaces through top and bottom surfaces of the substrate. Selective plating includes applying first and second metal patterns to a substrate surface, creating a potential voltage difference between the first metal pattern and a metal source, and plating the first metal pattern by attracting a first metal type to the voltage potential of the first metal pattern. The voltage potential of the first metal pattern is less than the voltage potential of the metal source.
    Type: Application
    Filed: September 30, 2003
    Publication date: April 14, 2005
    Inventors: Xiaowei Yao, Tam Nguyen, Marc Finot, Rickie Lake, Jeffrey Bennett, Robert Kohler
  • Patent number: 6821032
    Abstract: A low profile ringframe used in electro-optical module packaging is disclosed. The ringframe can be mounted so as to be set back from, be flush with, or be extending exteriorly over the outer end wall of the ceramic substrate, and may also be formed so as to help physically separate the ringframe-to-subtrate solder joint from the ringframe-to-laser weld seam. The ringframe, along the side where it is sealed to the adjacent substrate, can be notched with one or more cutout areas to allow a space for wicking of reflowed solder to prevent a built-up solder fillet from forming exteriorly of the ringframe.
    Type: Grant
    Filed: May 28, 2002
    Date of Patent: November 23, 2004
    Assignee: Intel Corporation
    Inventors: Rickie C. Lake, Xiaowei Yao, Charles E. Askew, Marc Epitaux, Marc A. Finot, Jeffrey A. Bennett, Robert M. Kohler, Jean-Marc Verdiell
  • Publication number: 20040062494
    Abstract: Optoelectronic packages with one or more feed-throughs having a cutout allow optical fibers that have been coupled to a component (e.g., an optical component, an electrical component, a structural component) to be fed through more easily than a package having feed-throughs without a cutout. In one embodiment, the cut in the feed-through is on the opposite side of the initial direction of the threading. That is, if the fiber is to come from above the feed-through, the cut is placed on the bottom of the feed-through. The placement of the cut on the feed-through allows a fiber previously attached to a component to be fed through without excessive curvature of the fiber.
    Type: Application
    Filed: September 30, 2002
    Publication date: April 1, 2004
    Inventors: Marc A. Finot, Xiaowei Yao
  • Publication number: 20030223709
    Abstract: A low profile ringframe used in electro-optical module packaging, for being hermetically sealed, e.g., by a solder joint, to a metalized ceramic substrate base, and to which a deep cover is later hermetically sealed, e.g., by a laser weld, the ringframe's side walls being of sufficiently low height to permit computer-aided viewing from the side, as well as top, of the critical optical fiber end-to-laser diode alignment. The ringframe can be mounted so as to be set back from, be flush with, or be extending exteriorly over the outer end wall of the ceramic substrate, and may also be formed so as to help physically separate the ringframe-to-substrate solder joint from the ringframe-to-laser weld seam. The ringframe, along the side where it is sealed to the adjacent substrate, can be notched with one or more cutout areas to allow a space for wicking of reflowed solder to prevent a built-up solder fillet from forming exteriorly of the ringframe.
    Type: Application
    Filed: May 28, 2002
    Publication date: December 4, 2003
    Inventors: Rickie C. Lake, Xiaowei Yao, Charles E. Askew, Marc Epitaux, Marc A. Finot, Jeffrey A. Bennett, Robert M. Kohler, Jean-Marc Verdiell