Abstract: Methods, systems, and devices for wireless communications are described. The method may involve a first user equipment (UE) receiving an indication of a set of sidelink resources and an indication of a set of uplink resources for transmitting sidelink feedback information. The first UE may receive a sidelink shared channel transmission from a second UE and upon receiving the sidelink shared transmission, generate feedback information regarding the sidelink shared channel transmission and transmit the feedback information directly to the base station using the set of uplink resources.

Abstract: A display module includes a display panel and a peripheral region. The peripheral region includes a bendable fan-out region including a panel bonding portion and a driving chip; a flexible circuit board, including a first and a second conductive layers, and a substrate. The first conductive layer includes a first and a second bonding portions, and a connection portion; the second conductive layer is located on a side of the first conductive layer and at least partially overlaps with the first bonding portion; the first and the second conductive layers are connected through a via hole penetrating through the substrate; an end of the flexible circuit board is bonded to the panel bonding portion through the first bonding portion, and the second bonding portion is bonded to a control circuit board; and a conductive protection layer, covering the driving chip and connected to the second conductive layer.

Abstract: Disclosed are an image processing method, a terminal and a non-transitory computer-readable storage medium. The image processing method includes: acquiring and detecting a first image, and determining whether the first image has a face image; in response that the first image has a face image, acquiring image information of a face region where the face image is located in the first image, and calculating an average brightness in the face region based on the image information; adjusting a brightness in the face region based on the average brightness and a preset model; acquiring parameter information of each pixel in the face region, and adjusting the parameter information of each pixel based on the parameter information and a preset rule, and generating a second image; and superimposing the first image and the second image, generating and displaying a third image.

Abstract: Disclosed is a white balance control method, including: acquiring a target pixel value of a target white point in a target image; calculating a target pixel sum value corresponding to a preset color temperature zone by using the target pixel value; obtaining a pixel gain value based on the target pixel sum value and a preset weight corresponding to the preset color temperature zone; and performing white balance adjustment on the target image by using the pixel gain value to obtain a result image. The present disclosure also provides a white balance control apparatus, a terminal device and a computer readable storage medium.

Abstract: Disclosed are an image processing method, a terminal and a non-transitory computer-readable storage medium. The image processing method includes: acquiring and detecting a first image, and determining whether the first image has a face image; in response that the first image has a face image, acquiring image information of a face region where the face image is located in the first image, and calculating an average brightness in the face region based on the image information; adjusting a brightness in the face region based on the average brightness and a preset model; acquiring parameter information of each pixel in the face region, and adjusting the parameter information of each pixel based on the parameter information and a preset rule, and generating a second image; and superimposing the first image and the second image, generating and displaying a third image.

Abstract: In some embodiments, an apparatus includes a processor configured to receive a set of digital samples associated with a set of optical signals received at a coherent optical receiver. The set of digital samples is associated with a set of optical channels. Each optical channel from the set of optical channels is spaced from at least one adjacent optical channel from the plurality of optical channels. The processor is configured to calculate, for each optical channel from the set of optical channels, a spacing between that optical channel and at least one adjacent optical channel from the set of optical channels based on digital signal processing of the set of digital samples. The processor is configured to send a signal indicating, for each optical channel from the set of optical channels, the spacing between that optical channel and the at least one adjacent optical channel.

Abstract: In some embodiments, an apparatus includes a processor configured to receive a set of digital samples associated with a set of optical signals received at a coherent optical receiver. The set of digital samples is associated with a set of optical channels. Each optical channel from the set of optical channels is spaced from at least one adjacent optical channel from the plurality of optical channels. The processor is configured to calculate, for each optical channel from the set of optical channels, a spacing between that optical channel and at least one adjacent optical channel from the set of optical channels based on digital signal processing of the set of digital samples. The processor is configured to send a signal indicating, for each optical channel from the set of optical channels, the spacing between that optical channel and the at least one adjacent optical channel.

Abstract: In some embodiments, an apparatus includes a processor configured to receive a set of digital samples associated with a set of optical signals received at a coherent optical receiver. The set of digital samples is associated with a set of optical channels. Each optical channel from the set of optical channels is spaced from at least one adjacent optical channel from the plurality of optical channels. The processor is configured to calculate, for each optical channel from the set of optical channels, a spacing between that optical channel and at least one adjacent optical channel from the set of optical channels based on digital signal processing of the set of digital samples. The processor is configured to send a signal indicating, for each optical channel from the set of optical channels, the spacing between that optical channel and the at least one adjacent optical channel.

Abstract: In some embodiments, an apparatus includes a processor configured to receive a set of digital samples associated with a set of optical signals received at a coherent optical receiver. The set of digital samples is associated with a set of optical channels. Each optical channel from the set of optical channels is spaced from at least one adjacent optical channel from the plurality of optical channels. The processor is configured to calculate, for each optical channel from the set of optical channels, a spacing between that optical channel and at least one adjacent optical channel from the set of optical channels based on digital signal processing of the set of digital samples. The processor is configured to send a signal indicating, for each optical channel from the set of optical channels, the spacing between that optical channel and the at least one adjacent optical channel.

Abstract: This disclosure provides a method and apparatus for detecting a transition of a memory cell current from a first state to a second state. An example apparatus includes a memory cell, a supplemental current source, a comparator, a reference voltage and a reference current source in a configuration that allows for real time detection of the transition of a memory cell. Detection of a memory cell current transition is captured when the output of the comparator transitions from one state to a second state in response to a sensing voltage exceeding the reference voltage.

Abstract: A multi-core processor is presented. The multi-core processor includes a first spin transfer torque magnetoresistive random-access memory (STT-MRAM) cache associated with a first core of the multi-core processor and tuned according to first attributes and a second STT-MRAM cache associated with a second core of the multi-core processor and tuned according to second attributes.

Abstract: Some implementations provide an interposer that includes a substrate, a first passive device in the substrate, and a second passive device. The first passive device includes a first set of through substrate vias (TSVs) in the substrate. The second passive device is configured to wirelessly couple to the first passive device. In some implementations, the second passive device includes a second set of through substrate vias (TSVs) in the substrate. In some implementations, the second passive device is configured to inductively couple to the first passive device. In some implementations, the first passive device is a first inductor and the second passive device is a second inductor. In some implementations, the interposer further includes a first set of interconnects coupled to the first set of TSVs, and a second set of interconnects coupled to the second set of TSVs.

Abstract: In one embodiment, a cache memory includes a cache array including a plurality of entries for caching cache lines of data, where the plurality of entries are distributed between a first region implemented in a first memory technology and a second region implemented in a second memory technology. The cache memory further includes a cache directory of the contents of the cache array and a cache controller that controls operation of the cache memory.

Abstract: Some implementations provide an interposer that includes a substrate, a first passive device in the substrate, and a second passive device. The first passive device includes a first set of through substrate vias (TSVs) in the substrate. The second passive device is configured to wirelessly couple to the first passive device. In some implementations, the second passive device includes a second set of through substrate vias (TSVs) in the substrate. In some implementations, the second passive device is configured to inductively couple to the first passive device. In some implementations, the first passive device is a first inductor and the second passive device is a second inductor. In some implementations, the interposer further includes a first set of interconnects coupled to the first set of TSVs, and a second set of interconnects coupled to the second set of TSVs.

Abstract: A multi-core processor is presented. The multi-core processor includes a first spin transfer torque magnetoresistive random-access memory (STT-MRAM) cache associated with a first core of the multi-core processor and tuned according to first attributes and a second STT-MRAM cache associated with a second core of the multi-core processor and tuned according to second attributes.

Abstract: In one embodiment, a cache memory includes a cache array including a plurality of entries for caching cache lines of data, where the plurality of entries are distributed between a first region implemented in a first memory technology and a second region implemented in a second memory technology. The cache memory further includes a cache directory of the contents of the cache array and a cache controller that controls operation of the cache memory.