Abstract: A configurable control loop arrangement for forming a control loop of a DC-DC converter that is configured to generate a control signal to control the DC-DC converter, the configurable control loop arrangement comprising: a digital-to-analog converter; a comparator; a timer configured to provide a timing-signal for controlling one or more of: the comparator in the determination of the comparison signal; the application of the comparison signal to a configurable-event-generation-logic-module; and the operation of the configurable-event-generation-logic-module; wherein the configurable-event-generation-logic-module comprises a flip-flop circuit, and wherein the configurable-event-generation-logic-module, when implemented in the control loop, is configured to provide for generation of the control signal based on the comparison signal, the timing-signal and a selected mode of the flip-flop circuit, and wherein the control signal is for application to one or more switches of the DC-DC converter.

Abstract: A configurable control loop arrangement for forming a control loop of a DC-DC converter that is configured to generate a control signal to control the DC-DC converter, the configurable control loop arrangement comprising: a digital-to-analog converter; a comparator; a timer configured to provide a timing-signal for controlling one or more of: the comparator in the determination of the comparison signal; the application of the comparison signal to a configurable-event-generation-logic-module; and the operation of the configurable-event-generation-logic-module; wherein the configurable-event-generation-logic-module comprises a flip-flop circuit, and wherein the configurable-event-generation-logic-module, when implemented in the control loop, is configured to provide for generation of the control signal based on the comparison signal, the timing-signal and a selected mode of the flip-flop circuit, and wherein the control signal is for application to one or more switches of the DC-DC converter.

Abstract: An integrated circuit includes on-chip flash memory, a EEPROM, cache memory, and a repair controller. When a defective address is detected in the flash memory, data slotted to be stored at the defective address is stored in the EEPROM by the repair controller. The cache memory includes a content addressable memory (CAM) that checks read addresses with the defective memory address and if there is a match, the data stored in the EEPROM is moved to the cache so that it can be output in place of data stored at the defective location of the flash memory. The memory repair system does not require any fuses nor is the flash required to include redundant rows or columns. Further, defective addresses can be detected and repaired on-the-fly.

Abstract: A system for reducing stress on a memory device that has multiple memory blocks. The system includes a counting unit for incrementing count values respectively associated with the memory blocks. Each of the count values indicates the number of times the associated memory block has been erased. A controller monitors the count values. Upon detecting that a count value associated with a first memory block reaches a predefined threshold, the controller selects a second memory block from the memory blocks to be swapped with the first memory block based on a count value associated with the second memory block.

Abstract: A system for reducing stress on a memory device that has multiple memory blocks. The system includes a counting unit for incrementing count values respectively associated with the memory blocks. Each of the count values indicates the number of times the associated memory block has been erased. A controller monitors the count values. Upon detecting that a count value associated with a first memory block reaches a predefined threshold, the controller selects a second memory block from the memory blocks to be swapped with the first memory block based on a count value associated with the second memory block.

Abstract: A power management circuit for integrated circuits operating systems where the power supply may be marginal includes a supply voltage characterization circuit and a clock synthesis circuit. The supply voltage characterization circuit determines the strength of the supply voltage applied to the IC and provides information to the synthesis circuit that is used to adjust the clock frequency of the IC to insure the IC does not draw too much current and force the IC into reset. A counter is used to determine the time between when the supply voltage reaches a first level and a second higher level, the time being representative of the slope of the supply voltage. Knowledge of the characteristics of a portion of the circuit under certain operating or benchmark conditions may be used to adjust the characterization.

Abstract: A power management circuit for integrated circuits operating systems where the power supply may be marginal includes a supply voltage characterization circuit and a clock synthesis circuit. The supply voltage characterization circuit determines the strength of the supply voltage applied to the IC and provides information to the synthesis circuit that is used to adjust the clock frequency of the IC to insure the IC does not draw too much current and force the IC into reset. A counter is used to determine the time between when the supply voltage reaches a first level and a second higher level, the time being representative of the slope of the supply voltage. Knowledge of the characteristics of a portion of the circuit under certain operating or benchmark conditions may be used to adjust the characterization.

Abstract: A low power State Retention Power Gating (SRPG) cell has a retention component and a non-retention component, and is operable in a run state, a first retention state, and a second retention state. In the run state, the retention and non-retention components are powered with a supply voltage. In the first retention state, the retention component is powered at the same supply voltage as in the run state, and the non-retention component is powered down. In the second retention state, the retention component is powered at a lower supply voltage than in the run state, and the non-retention component is powered down.

Abstract: An electronic device has a power control module for causing selected functional blocks to run in a low power mode of operation, while leaving other functional blocks supplied continuously with power. A power mode control distribution network includes serially connected chains of buffers in a distribution tree for distributing power mode control signals received at a common input end to respective output ends which are connected to respective functional blocks. In the low power mode of operation the power control module causes power to be supplied continuously to output buffers at the output ends of the chains while causing power supplied to other buffers to be reduced or cut-off. The output buffers include feedback paths for causing the states of the output buffers prior to the low power mode of operation to latch during the low power mode of operation.

Abstract: A low power State Retention Power Gating (SRPG) cell has a retention component and a non-retention component, and is operable in a run state, a first retention state, and a second retention state. In the run state, the retention and non-retention components are powered with a supply voltage. In the first retention state, the retention component is powered at the same supply voltage as in the run state, and the non-retention component is powered down. In the second retention state, the retention component is powered at a lower supply voltage than in the run state, and the non-retention component is powered down.

Abstract: An electronic device has a power control module for causing selected functional blocks to run in a low power mode of operation, while leaving other functional blocks supplied continuously with power. A power mode control distribution network includes serially connected chains of buffers in a distribution tree for distributing power mode control signals received at a common input end to respective output ends which are connected to respective functional blocks. In the low power mode of operation the power control module causes power to be supplied continuously to output buffers at the output ends of the chains while causing power supplied to other buffers to be reduced or cut-off. The output buffers include feedback paths for causing the states of the output buffers prior to the low power mode of operation to latch during the low power mode of operation.