Patents by Inventor Xiaoxiang Zhang
Xiaoxiang Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10141423Abstract: The disclosure provides a thin film transistor (TFT) and a fabrication method thereof, an array substrate and a fabrication method thereof, and a display apparatus. The fabrication method of a TFT includes: forming a protection layer in an area on an active layer between a source electrode and a drain electrode to be formed, forming a source-drain metal layer above the active layer having the protection layer formed thereon, coating a photoresist on the source-drain metal layer, and forming a photoresist reserved area corresponding to areas of the source electrode and the drain electrode to be formed and a photoresist non-reserved area corresponding to the other area; etching off the source-drain metal layer corresponding to the photoresist non-reserved area to form the source and drain electrodes and expose the protection layer above the active layer; and removing the photoresist above the source and drain electrodes and the protection layer.Type: GrantFiled: July 1, 2016Date of Patent: November 27, 2018Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.Inventors: Huibin Guo, Xiaoxiang Zhang, Jing Wang
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Patent number: 10140911Abstract: The present application discloses a shift register unit for outputting a gate driving signal to control image display in an operation cycle including sequentially an input phase, an output phase, an output-suspending phase, the shift register unit including a first node-control circuit connected to a pull-up node and a first pull-down node; a second node-control circuit connected to a pull-down control node and the pull-up node; a pull-up circuit connected to the pull-up node, a first input terminal for receiving a first clock signal, and an output terminal for outputting the gate driving signal, and configured to control the first clock signal to be passed from the first input terminal to the output terminal when the pull-up node is at a first potential level; a third node-control circuit connected to the pull-up node, the first pull-down node, the pull-down control node, and a second input terminal for receiving a second clock signal; and configured to control the first pull-down node to receive the secondType: GrantFiled: September 22, 2016Date of Patent: November 27, 2018Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.Inventors: Xiaoxiang Zhang, Zheng Liu, Mingxuan Liu, Huibin Guo, Xi Chen
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Publication number: 20180226476Abstract: An array panel and a manufacturing method thereof, a display panel and a display device are provided. The manufacturing method includes: forming first conducting patterns, second conducting patterns and metal connection lines on a base substrate, the metal connection lines being connected to the first conducting patterns and the second conducting patterns; and etching the metal connection lines so as to isolate the first conducting patterns from the second conducting patterns.Type: ApplicationFiled: October 30, 2015Publication date: August 9, 2018Inventors: Zhichao ZHANG, Tsung Chieh KUO, Zheng LIU, Xiaoxiang ZHANG, Xi CHEN, Mingxuan LIU
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Publication number: 20180211606Abstract: A shift register circuit and a driving method therefor, a gate line driving circuit and an array substrate, the shift register circuit includes: a charging sub-circuit for charging a pull-up node under the control of a signal input by an input signal terminal; an output sub-circuit for outputting, through an output terminal, a clock signal provided by a first clock signal terminal to serve as a drive signal, under control of an electric level of the pull-up node; a first pull-down sub-circuit for pulling down the pull-up node and the output terminal under the control of an electric level of a first pull-down node; and a reset sub-circuit for resetting the pull-up node and the output terminal under the control of a reset signal input by a reset signal terminal.Type: ApplicationFiled: May 26, 2017Publication date: July 26, 2018Inventors: Xiaoxiang ZHANG, Zheng LIU, Huibin GUO, Mingxuan LIU
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Publication number: 20180203281Abstract: A manufacturing method of a metal layer, a functional substrate and a manufacturing method thereof, and a display device are provided. The manufacturing method of a metal layer includes: forming an insulating layer on a base substrate; forming an etching buffer layer on the insulating layer; patterning the etching buffer layer and the insulating layer to form a plurality of recessed microstructures in the insulating layer; stripping the etching buffer layer; and forming a metal layer on the insulating layer, a surface of the metal layer adjacent to the insulating layer is formed with a plurality of protruded portions which are filled into the plurality of recessed microstructures. The manufacturing method of a metal layer may form a metal layer with anti-reflection effect.Type: ApplicationFiled: January 3, 2017Publication date: July 19, 2018Inventors: Xiaoxiang ZHANG, Liping LUO, Mingxuan LIU, Huibin GUO, Zhichao ZHANG
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Publication number: 20180190795Abstract: The present disclosure provides an array substrate, the array substrate being divided into a plurality of pixel units, each of which is provided with a thin film transistor therein, the thin film transistor comprising an active layer and a passivation layer, a source and a drain arranged on the active layer, wherein the passivation layer is formed with a source via hole penetrating the passivation layer, a drain via hole penetrating the passivation layer, and a data line slot communicated with the source via hole; the source is arranged in the source via hole to be connected with the active layer; the drain is arranged in the drain via hole to be connected with the active layer; a data line is arranged in the data line slot to be electrically connected with corresponding source. The present disclosure also provides a manufacturing method of an array substrate and a display device.Type: ApplicationFiled: March 27, 2017Publication date: July 5, 2018Inventors: Zheng LIU, Zhichao ZHANG, Xi CHEN, Xiaoxiang ZHANG, Mingxuan LIU
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Patent number: 10012906Abstract: A developing device includes a spraying assembly and a concentration regulating assembly. A developing method usable in the developing device includes: spraying developing agents by a spraying assembly onto respective developing regions on a substrate to be developed; and spraying a regulating liquid by a concentration regulating assembly onto a target developing region on the substrate to be developed to change concentration of the developing agents.Type: GrantFiled: July 12, 2017Date of Patent: July 3, 2018Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.Inventors: Liping Luo, Mingxuan Liu, Xiaoxiang Zhang, Huishuang Liu, Zengbiao Sun, Wei Li
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Publication number: 20180144677Abstract: The present application discloses a shift register unit for outputting a gate driving signal to control image display in an operation cycle including sequentially an input phase, an output phase, an output-suspending phase, the shift register unit including a first node-control circuit connected to a pull-up node and a first pull-down node; a second node-control circuit connected to a pull-down control node and the pull-up node; a pull-up circuit connected to the pull-up node, a first input terminal for receiving a first clock signal, and an output terminal for outputting the gate driving signal, and configured to control the first clock signal to be passed from the first input terminal to the output terminal when the pull-up node is at a first potential level; a third node-control circuit connected to the pull-up node, the first pull-down node, the pull-down control node, and a second input terminal for receiving a second clock signal; and configured to control the first pull-down node to receive the secondType: ApplicationFiled: September 22, 2016Publication date: May 24, 2018Applicants: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.Inventors: Xiaoxiang Zhang, Zheng Liu, Mingxuan Liu, Huibin Guo, Xi Chen
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Publication number: 20180130127Abstract: This disclosure relates generally to systems and methods for providing personalized financing information and, more particularly, systems and methods for providing personalized financing information via a dealership website using an API associated with a financial service provider. In one embodiment, a system includes memory hardware storing instructions that configure processing hardware to receive a loan request for a buyer via a real-time API that includes at least buyer identification and financial information and information associated at least one inventory item presented on a dealership website. The system may also determine financing information comprising prospective financing terms for the at least one item based on at least the loan request. The server may also provide, to the dealership server via the real-time API, the determined financing information for presentation on the dealership website, including prospective financing terms information corresponding to each of the at least one item.Type: ApplicationFiled: January 4, 2018Publication date: May 10, 2018Applicant: CAPITAL ONE FINANCIAL CORPORATIONInventors: Katherine Forrester, Nicholas Dolle, Xiaoxiang Zhang, Kurt Johnson, Jeffrey Whalen, David Gray, Shaun Webb, Maninder Suri, Ruhaab Markas
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Publication number: 20180108756Abstract: The disclosure provides a thin film transistor (TFT) and a fabrication method thereof, an array substrate and a fabrication method thereof, and a display apparatus. The fabrication method of a TFT includes: forming a protection layer in an area on an active layer between a source electrode and a drain electrode to be formed, forming a source-drain metal layer above the active layer having the protection layer formed thereon, coating a photoresist on the source-drain metal layer, and forming a photoresist reserved area corresponding to areas of the source electrode and the drain electrode to be formed and a photoresist non-reserved area corresponding to the other area; etching off the source-drain metal layer corresponding to the photoresist non-reserved area to form the source and drain electrodes and expose the protection layer above the active layer; and removing the photoresist above the source and drain electrodes and the protection layer.Type: ApplicationFiled: July 1, 2016Publication date: April 19, 2018Applicants: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.Inventors: Huibin GUO, Xiaoxiang ZHANG, Jing WANG
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Publication number: 20180089757Abstract: Methods and systems are disclosed for providing approved financing in advance of a purchase to a buyer of an item, such as an automobile, and allowing the prospective buyer to maintain control over the financing throughout the sales process. According to disclosed embodiments, a financial service system configures a financing website for the buyer, and receives personal information as well as information relating to the desired item. The financial service system approves loan parameters for the buyer, and provides the user with a link to access the financing website on a mobile device while at a dealership. Financing parameters can thus be edited throughout the process until the final sales agreement, providing the buyer with confidence and flexibility in the buying process.Type: ApplicationFiled: November 30, 2017Publication date: March 29, 2018Inventors: Katherine D. Forrester, Patrick A. Eberle, Nicholas Dolle, Steven G. Chiagouris, JoAnna R. Hartzmark, Xiaoxiang Zhang, Kurt Johnson, Kenneth S. Childs
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Patent number: 9899430Abstract: Embodiments of the present disclosure provide a GOA unit and a method for producing the same and a gate driver circuit, which are directed to a field of display technique. The GOA unit includes: a TFT module and a capacitor structure formed on a substrate. The TFT module includes a gate electrode, a source electrode and a drain electrode, and the capacitor structure includes a first electrode and a second electrode configured to form a first capacitor. The gate of the TFT module is located in a same layer as the first electrode of the capacitor structure, the source electrode and the drain electrode of the TFT module are located in a same layer as the second electrode of the capacitor structure, and the second electrode has a groove. Embodiments of the present application are used for a display apparatus.Type: GrantFiled: April 4, 2016Date of Patent: February 20, 2018Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.Inventors: Xiaoxiang Zhang, Tsung Chieh Kuo, Zheng Liu, Zhichao Zhang, Mingxuan Liu, Xi Chen
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Patent number: 9899225Abstract: An embodiment of present disclosure provides a method for manufacturing an array substrate, an array substrate manufactured by the method, and a mask. The method for manufacturing the array substrate includes: providing a mask including a transparent substrate, a light semi-transmission region, a light non-transmission region, and a light transmission region excluding the light semi-transmission region and the light non-transmission region being formed on the transparent substrate; forming a first mask pattern on a base substrate by means of the light non-transmission region of the mask; and forming a second mask pattern on the base substrate having the first mask pattern by means of the light semi-transmission region and the light non-transmission region of the mask.Type: GrantFiled: September 10, 2015Date of Patent: February 20, 2018Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO. LTD.Inventors: Zhichao Zhang, Tsung-Chieh Kuo, Zheng Liu, Xiaoxiang Zhang, Xi Chen, Mingxuan Liu
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Publication number: 20180017871Abstract: The present disclosure provides a developing device and a developing method. The method may be used in the developing device. The developing device includes a spraying assembly and a concentration regulating assembly. The method includes: spraying developing agents by a spraying assembly onto respective developing regions on a substrate to be developed; and spraying a regulating liquid by a concentration regulating assembly onto a target developing region on the substrate to be developed to change concentration of the developing agents.Type: ApplicationFiled: July 12, 2017Publication date: January 18, 2018Inventors: Liping Luo, Mingxuan Liu, Xiaoxiang Zhang, Huishuang Liu, Zengbiao Sun, Wei Li
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Patent number: 9761617Abstract: A method for manufacturing an array substrate comprises: forming a pixel electrode and a gate of a thin film transistor on a substrate; forming a gate insulating layer; forming an active layer and a source and a drain, which are provided on the active layer, of the thin film transistor by a patterning process; forming a passivation layer; forming a main via penetrating through the gate insulating layer and the passivation layer and a main-via extension portion under a portion of the drain by a patterning process, wherein the main via is connected to the main-via extension portion; removing a portion of the drain which protrudes above the main-via extension portion so as to form a final via; and forming a connection electrode and a common electrode, wherein the connection electrode electrically connects the drain to the pixel electrode through the final via.Type: GrantFiled: January 14, 2016Date of Patent: September 12, 2017Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.Inventors: Zheng Liu, Tsung Chieh Kuo, Xi Chen, Xiaoxiang Zhang, Zhichao Zhang, Mingxuan Liu
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Patent number: 9721979Abstract: A method for manufacturing an array substrate comprises: forming a pixel electrode and a gate of a thin film transistor on a substrate; forming a gate insulating layer; forming an active layer and a source and a drain, which are provided on the active layer, of the thin film transistor by a patterning process; forming a passivation layer; forming a main via penetrating through the gate insulating layer and the passivation layer and a main-via extension portion under a portion of the drain by a patterning process, wherein the main via is connected to the main-via extension portion; removing a portion of the drain which protrudes above the main-via extension portion so as to form a final via; and forming a connection electrode and a common electrode, wherein the connection electrode electrically connects the drain to the pixel electrode through the final via.Type: GrantFiled: January 14, 2016Date of Patent: August 1, 2017Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.Inventors: Zheng Liu, Tsung Chieh Kuo, Xi Chen, Xiaoxiang Zhang, Zhichao Zhang, Mingxuan Liu
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Patent number: 9710089Abstract: A touch display panel, a manufacturing method thereof, a driving method and a touch display device are disclosed. The touch display panel comprises an array substrate and a color film substrate, wherein the array substrate comprises a first thin film transistor and a first detection line formed on a first substrate, and the color film substrate comprises a main spacer, an auxiliary spacer, a reference signal line and a second detection line formed on a second substrate. The bottom of the main spacer is connected to the reference signal line, the top of the main spacer is connected to a first source, the bottom of the auxiliary spacer is connected to the second detection line, and a projection of the top of the auxiliary spacer on the array substrate connects a first drain with the first detection line.Type: GrantFiled: July 16, 2015Date of Patent: July 18, 2017Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.Inventors: Xi Chen, Jinchao Bai, Zheng Liu, Xiaoxiang Zhang, Mingxuan Liu, Zhichao Zhang
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Publication number: 20170200749Abstract: A method for manufacturing an array substrate comprises: forming a pixel electrode and a gate of a thin film transistor on a substrate; forming a gate insulating layer; forming an active layer and a source and a drain, which are provided on the active layer, of the thin film transistor by a patterning process; forming a passivation layer; forming a main via penetrating through the gate insulating layer and the passivation layer and a main-via extension portion under a portion of the drain by a patterning process, wherein the main via is connected to the main-via extension portion; removing a portion of the drain which protrudes above the main-via extension portion so as to form a final via; and forming a connection electrode and a common electrode, wherein the connection electrode electrically connects the drain to the pixel electrode through the final via.Type: ApplicationFiled: January 14, 2016Publication date: July 13, 2017Inventors: Zheng LIU, Tsung Chieh KUO, Xi CHEN, Xiaoxiang ZHANG, Zhichao ZHANG, Mingxuan LIU
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Publication number: 20170125250Abstract: An embodiment of present disclosure provides a method for manufacturing an array substrate, an array substrate manufactured by the method, and a mask. The method for manufacturing the array substrate includes: providing a mask including a transparent substrate, a light semi-transmission region, a light non-transmission region, and a light transmission region excluding the light semi-transmission region and the light non-transmission region being formed on the transparent substrate; forming a first mask pattern on an base substrate by means of the light non-transmission region of the mask; and forming a second mask pattern on the base substrate having the first mask pattern by means of the light semi-transmission region and the light non-transmission region of the mask.Type: ApplicationFiled: September 10, 2015Publication date: May 4, 2017Inventors: Zhichao Zhang, Tsung-Chieh Kuo, Zheng Liu, Xiaoxiang Zhang, Xi Chen, Mingxuan Liu
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Publication number: 20160372629Abstract: The present invention provides a manufacturing method for a light barrier substrate which comprising steps of: forming a metal electrode pattern on a substrate through a first patterning process; forming an insulating layer above the substrate and the metal electrode pattern; forming a metal electrode via hole on the insulating layer and forming a channel pattern for a connecting line between a metal electrode and an exterior integrated circuit (IC) on the insulating layer, with a half tone make process, through a second patterning process; forming a transparent electrode layer pattern on the substrate on which the metal electrode via hole and the channel pattern are formed.Type: ApplicationFiled: July 29, 2014Publication date: December 22, 2016Inventors: Xiaoxiang Zhang, Zheng Liu, Zongjie Guo