Abstract: Provided are a solar cell, a method for preparing the same, and a photovoltaic module. The solar cell includes a silicon substrate, a tunneling passivation contact structure, and a second electrode. The silicon substrate includes a first surface and a second surface. The second surface includes first regions and second regions that are alternately arranged. A tunneling passivation is disposed on the second surface in the first region. The tunneling passivation contact structure includes a tunneling layer, a second doped layer, a blocking layer, and a third doped layer that are sequentially disposed on the second surface. A doping type of the second doped layer and the third doped layer are identical to a doping type of the silicon substrate. The second electrode is disposed in the second region and in contact with the third doped layer.

Abstract: Provided is a solar cell. The solar cell includes a silicon substrate, a P-type doping structure located on the back surface of the silicon substrate, an N-type doping structure located on the back surface of the silicon substrate, a spacing region located between the P-type doping structure and the N-type doping structure, a first electrode located on a back surface of the P-type doping structure, and a second electrode located on a back surface of the N-type doping structure. In a first direction, the back surface of the P-type doping structure is higher than the back surface of the N-type doping structure, and the first direction is from a front surface of the silicon substrate to the back surface of the silicon substrate. With the solar cell of the present disclosure, more carriers can be generated and successfully collected, improving a cell efficiency.

Abstract: A solar cell and a preparation method thereof, and a photovoltaic module. The solar cell includes a silicon substrate including a first surface and a second surface that includes first and second regions. A first tunneling and passivation contact structure is provided on the first region, a second passivation structure is provided on the first and the second regions. The second passivation structure on the first region is disposed on the first tunneling and passivation contact structure. A height difference between portions of a surface of the second passivation structure at a side facing away from the substrate on the first region and on the second region is 0.01 ?m to 8 ?m, and/or a height difference between portions of a surface of the second passivation structure at a side facing towards the substrate on the first region and on the second region is 0.01 ?m to 8 ?m.

Abstract: The present disclosure relates to a method for preparing nano-textured surface on single side of a silicon wafer, including the following steps: (1) superimposing two silicon wafers to obtain a first silicon wafer superimposition structure; the side on which the silicon wafers is superimposed is recorded as an attached surface, and the side exposed outside is recorded as an exposed surface; and (2) performing nano-textured surface etching on the first silicon wafer superimposition structure; and providing each silicon wafer with nano-textured surface on the exposed surface and a nano-textured surface etched strip on the edge of the attached surface. In the present disclosure, while the nano-textured surface etching is performed, the edge of the attached surface is etched with nano-textured surface by selecting a specific etching rate, which reduces the pulling force for detaching the wafers and reduces the fragmentation rate during the detaching process.

Abstract: The present disclosure relates to a method for preparing nano-textured surface on single side of a silicon wafer, including the following steps: (1) superimposing two silicon wafers to obtain a first silicon wafer superimposition structure; the side on which the silicon wafers is superimposed is recorded as an attached surface, and the side exposed outside is recorded as an exposed surface; and (2) performing nano-textured surface etching on the first silicon wafer superimposition structure; and providing each silicon wafer with nano-textured surface on the exposed surface and a nano-textured surface etched strip on the edge of the attached surface. In the present disclosure, while the nano-textured surface etching is performed, the edge of the attached surface is etched with nano-textured surface by selecting a specific etching rate, which reduces the pulling force for detaching the wafers and reduces the fragmentation rate during the detaching process.