Abstract: A secured payment method, secured payment device and computer-readable storage medium, relating to the technical field of Internet. The method comprises: detecting whether a mobile terminal is connected to a first secured payment module, wherein the first secured payment module shares a payment hardware interface with the mobile terminal; activating the payment hardware interface, if the detection result shows that the mobile terminal is connected to the first secured payment module; detecting whether the payment hardware interface is controlled by the first secured payment module or by the mobile terminal; providing a payment warning, if the detection result shows that the payment hardware interface is controlled by the mobile terminal. Thus, the manufacturing costs of the devices can be reduced, potential safety risk in some transaction can also be avoided, and a secured payment is guaranteed.

Abstract: A secured payment method, secured payment device and computer-readable storage medium, relating to the technical field of Internet. The method includes: detecting whether a mobile terminal is connected; if the detection result shows that a mobile terminal is connected, activating a payment hardware interface shared with the mobile terminal; detecting whether the payment hardware interface is controlled by the secured payment device or by the mobile terminal during a payment process; if the detection result shows that the payment hardware interface is controlled by the mobile terminal, providing a payment warning. Thereby, the manufacturing cost of the devices can be reduced, also, potential safety risk in some transaction can be avoided, and a secured payment is guaranteed.

Abstract: A method for secure payment, including: detecting whether a connected mobile terminal exists; acquiring, when the connected mobile terminal exists, a first user transaction information, and encrypting the first user transaction information to generate a corresponding first encrypted transaction information; sending the first encrypted transaction information to a transaction verification server based on a first hardware interface of the mobile terminal, and receiving a transaction verification result from the transaction verification server; and determining, according to the transaction verification result, whether a payment operation is to be performed.

Abstract: A tamper-proof structure and an electronic device are provided in the present application. The tamper-proof structure includes a first-order circuit board, at least one tamper-proof component, at least one safety signal wire and a security chip. The safety signal wire is wrapped around an outer layer of the first-order circuit board or penetrates through a through hole and is wrapped around an inner layer of the first-order circuit board to form a tamper-proof area as required. The safety signal wire is connected to a tamper-proof switch and the security chip correspondingly, and a level of the safety signal wire is changed when the tamper-proof switch or the safety signal wire is damaged, and the security chip is triggered to erase sensitive information accordingly. By punching on the first-order circuit board, an objective of tamper-proof and an objective of reduction of design cost and simplification of security solution are achieved simultaneously.

Abstract: A sensitive element protection mechanism and a payment device using the sensitive element protection mechanism includes a circuit board; a sensitive element configured for storing, transmitting and/or processing user account information and user transaction information; a shield arranged in parallel with the circuit board; and an elastic member connecting the circuit board and the shield. The sensitive element is located on a side of the circuit board near the shield. The circuit board and the shield are provided and the sensitive element is provided between the circuit board and the shield so as to protect the sensitive element through the shield. The elastic member connects the circuit board and the shield to prevent the circuit board from being separated from the shield, thus preventing the circuit board from being opened to steal sensitive information in the sensitive element.

Abstract: A hardware encryption housing and a payment device using the hardware encryption housing includes a top shell, a bottom shell, a circuit board and a trigger switch configured to transmit a trigger signal when the top shell is separated from the bottom shell. A security chip, mounted on the circuit board, has a storage module configured to store key information and a detection module configured to clear the key information and lock the security chip after the trigger signal is detected. The trigger signal is transmitted when the top shell is separated from the bottom shell, and the detection module is provided in the security chip to detect whether the trigger switch transmits a trigger signal. When detected, the key information in the storage module is cleared and the security chip is locked.

Abstract: The present invention relates to fusion proteins for the expression of G-protein coupled receptor proteins (GPCR) with the fusion partners, as inserted fragments, from mammalian cells. The fusion partners are from a fragment of APJ protein (“the APJ protein fragment”) or a fragment with homology of more than 90% similarity to the APJ protein fragment; or a fragment of RGS16 protein (the “RGS16 protein fragment”) or a fragment with homology of more than 90% similarity to the RGS16 protein fragment; or the fragment of DNJ protein (the “DNJ protein fragment”) or a fragment with homology of more than 90% similarity to DNJ protein fragment. The fusion expression of GPCR with the above mentioned fusion partners can improve the protein yield and stability when purified from cells. Therefore, these fusion protein partners can be widely used for the study of GPCR proteins.

Abstract: A sensitive element protection mechanism and a payment device using the sensitive element protection mechanism includes a circuit board; a sensitive element configured for storing, transmitting and/or processing user account information and user transaction information; a shield arranged in parallel with the circuit board; and an elastic member connecting the circuit board and the shield. The sensitive element is located on a side of the circuit board near the shield. The circuit board and the shield are provided and the sensitive element is provided between the circuit board and the shield so as to protect the sensitive element through the shield. The elastic member connects the circuit board and the shield to prevent the circuit board from being separated from the shield, thus preventing the circuit board from being opened to steal sensitive information in the sensitive element.

Abstract: A hardware encryption housing and a payment device using the hardware encryption housing includes a top shell, a bottom shell, a circuit board and a trigger switch configured to transmit a trigger signal when the top shell is separated from the bottom shell. A security chip, mounted on the circuit board, has a storage module configured to store key information and a detection module configured to clear the key information and lock the security chip after the trigger signal is detected. The trigger signal is transmitted when the top shell is separated from the bottom shell, and the detection module is provided in the security chip to detect whether the trigger switch transmits a trigger signal. When detected, the key information in the storage module is cleared and the security chip is locked.

Abstract: The present invention relates to fusion proteins for the expression of G-protein coupled receptor proteins (GPCR) with the fusion partners, as inserted fragments, from mammalian cells. The fusion partners are from a fragment of APJ protein (“the APJ protein fragment”) or a fragment with homology of more than 90% similarity to the APJ protein fragment; or a fragment of RGS16 protein (the “RGS16 protein fragment”) or a fragment with homology of more than 90% similarity to the RGS16 protein fragment; or the fragment of DNJ protein (the “DNJ protein fragment”) or a fragment with homology of more than 90% similarity to DNJ protein fragment. The fusion expression of GPCR with the above mentioned fusion partners can improve the protein yield and stability when purified from cells. Therefore, these fusion protein partners can be widely used for the study of GPCR proteins.

Abstract: The present invention relates to fusion proteins for the expression of G-protein coupled receptor proteins (GPCR) with the fusion partners, as inserted fragments, from mammalian cells. The fusion partners are from a fragment of APJ protein (“the APJ protein fragment”) or a fragment with homology of more than 90% similarity to the APJ protein fragment; or a fragment of RGS16 protein (the “RGS16 protein fragment”) or a fragment with homology of more than 90% similarity to the RGS16 protein fragment; or the fragment of DNJ protein (the “DNJ protein fragment”) or a fragment with homology of more than 90% similarity to DNJ protein fragment. The fusion expression of GPCR with the above mentioned fusion partners can improve the protein yield and stability when purified from cells. Therefore, these fusion protein partners can be widely used for the study of GPCR proteins.

Abstract: The present invention relates to fusion proteins for the expression of G-protein coupled receptor proteins (GPCR) with the fusion partners, as inserted fragments, from mammalian cells. The fusion partners are from a fragment of APJ protein (“the APJ protein fragment”) or a fragment with homology of more than 90% similarity to the APJ protein fragment; or a fragment of RGS16 protein (the “RGS16 protein fragment”) or a fragment with homology of more than 90% similarity to the RGS16 protein fragment; or the fragment of DNJ protein (the “DNJ protein fragment”) or a fragment with homology of more than 90% similarity to DNJ protein fragment. The fusion expression of GPCR with the above mentioned fusion partners can improve the protein yield and stability when purified from cells. Therefore, these fusion protein partners can be widely used for the study of GPCR proteins.

Abstract: The present invention relates to fusion proteins for the expression of G-protein coupled receptor proteins (GPCR) with the fusion partners, as inserted fragments, from mammalian cells. The fusion partners are from a fragment of APJ protein (“the APJ protein fragment”) or a fragment with homology of more than 90% similarity to the APJ protein fragment; or a fragment of RGS16 protein (the “RGS16 protein fragment”) or a fragment with homology of more than 90% similarity to the RGS16 protein fragment; or the fragment of DNJ protein (the “DNJ protein fragment”) or a fragment with homology of more than 90% similarity to DNJ protein fragment. The fusion expression of GPCR with the above mentioned fusion partners can improve the protein yield and stability when purified from cells. Therefore, these fusion protein partners can be widely used for the study of GPCR proteins.

Abstract: The present invention relates to fusion proteins for the expression of G-protein coupled receptor proteins (GPCR) with the fusion partners, as inserted fragments, from mammalian cells. The fusion partners are from a fragment of APJ protein (“the APJ protein fragment”) or a fragment with homology of more than 90% similarity to the APJ protein fragment; or a fragment of RGS16 protein (the “RGS16 protein fragment”) or a fragment with homology of more than 90% similarity to the RGS16 protein fragment; or the fragment of DNJ protein (the “DNJ protein fragment”) or a fragment with homology of more than 90% similarity to DNJ protein fragment. The fusion expression of GPCR with the above mentioned fusion partners can improve the protein yield and stability when purified from cells. Therefore, these fusion protein partners can be widely used for the study of GPCR proteins.

Abstract: Systems and methods are disclosed for employing an equalization technique that improves equalizer input sensitivity and which reduces power consumption. In particular, an equalization architecture is described that includes a continuous-time linear equalizer and a decision feedback equalizer, each with offset cancellation that enables the equalizer to be used at high data rates. In addition, the equalization structure has a power-saving mode for bypassing the decision feedback equalizer. These offset cancellation and power-saving features are enabled and controlled using programmable logic on a programmable device.

Abstract: Systems and methods are disclosed for employing an equalization technique that improves equalizer input sensitivity and which reduces power consumption. In particular, an equalization architecture is described that includes a continuous-time linear equalizer and a decision feedback equalizer, each with offset cancellation that enables the equalizer to be used at high data rates. In addition, the equalization structure has a power-saving mode for bypassing the decision feedback equalizer. These offset cancellation and power-saving features are enabled and controlled using programmable logic on a programmable device.

Abstract: Equalizer circuitry on an integrated circuit (“IC”) includes first, second, and third continuous time, equalizer stages connected in series. Each stage includes peaking inductor circuitry. The equalizer circuitry may further include controllably variable, static, DC mode offset voltage compensation circuitry and/or dynamic, continuous mode, offset voltage compensation circuitry for respectively reducing DC voltage offset and/or time-varying, continuous mode voltage offset between an output of the third equalizer stage and utilization circuitry to which that output is applied. The first equalizer stage may be preceded by termination circuitry having controllably variable impedance. Differential circuitry and signalling may be used for various circuit components. The equalizer circuitry is particularly useful for fabrication as part of a programmable IC, using 28 nm CMOS technology, and as a receiver equalizer for a high-speed serial data signal having a bit rate of 20-25 Gbps.

Abstract: A test driver transmitter drives a test signal through a resistive termination circuit to a first pin to test components on a board during a boundary scan test operation. A test receiver receives the test signal through a second pin and a pass gate coupled to the second pin during the boundary scan test operation. A test signal is transmitted to the test receiver during loopback operation through a loopback circuit.

Abstract: One embodiment relates to a continuous-time circuit configured with an offset cancellation loop. The continuous-time circuit includes a multi-stage amplifier chain, including a first amplifier stage and a last amplifier stage, and an offset cancellation loop. The offset cancellation loop is configured to receive an output of the last amplifier stage and to provide an offset correction voltage signal to the first amplifier stage. The offset compensation loop may create one dominant pole and a single consequential parasitic pole so as to have greater stability and may advantageously achieve a second-order roll-off in response magnitude at higher frequencies. Other embodiments, aspects, and features are also disclosed.

Abstract: One embodiment relates to a continuous-time circuit configured with an offset cancellation loop. The continuous-time circuit includes a multi-stage amplifier chain, including a first amplifier stage and a last amplifier stage, and an offset cancellation loop. The offset cancellation loop is configured to receive an output of the last amplifier stage and to provide an offset correction voltage signal to the first amplifier stage. The offset compensation loop may create one dominant pole and a single consequential parasitic pole so as to have greater stability and may advantageously achieve a second-order roll-off in response magnitude at higher frequencies. Other embodiments, aspects, and features are also disclosed.