Abstract: Embodiments provide a core network selection method, an apparatus, and a system. The method includes the following steps: obtaining first dedicated core network (DCN) information from an access network device, where the first DCN information includes information about at least one DCN that can be accessed by the access network device. The method also includes selecting a to-be-accessed DCN from the at least one DCN according to the first DCN information, and sending information about the to-be-accessed DCN to the access network device, so that the access network device determines a core network device according to the information about the to-be-accessed DCN.

Abstract: The present invention provides a method of aligning a quadrate wafer in a first photolithography process. The method includes: step A: fabricating mask aligning markers in a periphery region of a mask, which is used for a first exposure process of the quadrate wafer, around a mask pattern of the mask; step B: during the first exposure process, positioning the quadrate wafer in a preset region by using the mask aligning markers on the mask, and exposing the quadrate wafer through the mask; and step C: performing alignment for the quadrate wafer during a second exposure process and subsequent exposure processes by using aligning markers on the quadrate wafer that are obtained during the first exposure process. The method may be easily and reliably performed to ensure intact dies at periphery of a quadrate wafer to be produced and thus render increased yield of chips.

Abstract: The present disclosure involves a GaN-based Schottky diode rectifier and a method of manufacturing the same. The GaN-based Schottky diode rectifier includes: a substrate, on which a GaN intrinsic layer and a barrier layer are grown in turn; a p-type two-dimension electron gas depletion layer located on an upper surface of the barrier layer; a cathode electrode located at a position on the upper surface of the barrier layer where is different from the position where the p-type two-dimension electron gas depletion layer is formed; and an anode electrode including a first part and a second part electrically connected to each other.

Abstract: The present invention discloses a method of forming a polygon-sectional rodlike ingot having an orientation marker or rounded corners, a rodlike ingot and a sheet substrate so formed. The method comprises: selecting one of sides of the polygon-sectional rodlike ingot that is parallel to an axial direction thereof as a first feature of a surface orientation marker; forming a minisize notch, which is parallel to an edge, in the one of sides selected as the first feature in the axial direction of the rodlike ingot, as a second feature of the orientation marker; and processing the rodlike ingot to form rounded corners. The sheet substrate is obtained by cutting the rodlike ingot.

Abstract: The present invention provides a method of aligning a quadrate wafer in a first photolithography process. The method includes: step A: fabricating mask aligning markers in a periphery region of a mask, which is used for a first exposure process of the quadrate wafer, around a mask pattern of the mask; step B: during the first exposure process, positioning the quadrate wafer in a preset region by using the mask aligning markers on the mask, and exposing the quadrate wafer through the mask; and step C: performing alignment for the quadrate wafer during a second exposure process and subsequent exposure processes by using aligning markers on the quadrate wafer that are obtained during the first exposure process. The method may be easily and reliably performed to ensure intact dies at periphery of a quadrate wafer to be produced and thus render increased yield of chips.

Abstract: The present disclosure relates to a light emitting diode packaging structure and the method of manufacturing the same. The light emitting diode packaging structure has an insulating substrate with through holes formed on each side of the upper surface thereof, the through hole being filled with conductive metal. Additionally, a n-type layer, an active layer, a p-type layer, an insulating layer and a p-type electrode are formed on the insulating substrate. The structure further may include a n-type electrode provided on a side of the upper surface of the n-type layer; a first back electrode provided at one side of the back surface of the insulating substrate; a second back electrode provided at the other side of back surface of the insulating substrate; and an optical element packaged on the base substrate.

Abstract: The present disclosure relates to a light emitting diode packaging structure and the method of manufacturing the same.

Abstract: The present invention discloses A graphene film electrical current spreading layer applied GaN-based LED in vertical. structure, comprising: a p-type metal electrode including a metal support substrate and a metal reflective mirror formed on the metal support substrate; a hole injecting layer formed on the metal reflective mirror of the p-type metal electrode; an electron blocking layer formed on the hole injecting layer; a lighting layer formed on the electron blocking layer; an electron limiting layer formed on the lighting layer; an electron injecting layer formed on the electron limiting layer; an electrical current spreading layer formed on the electron injecting layer; two n-type metal electrodes formed on the electrical spreading layer and covering a part of the electrical current spreading layer.