Abstract: The present disclosure provides a camera apparatus, an SMA driving device and a manufacturing method, a driving method and a wiring method, wherein the SMA driving device further comprises a lens carrier, at least one upgoing driver, and at least one downgoing driver; wherein the lens carrier is drivingly connected to the upgoing driver, and the upgoing driver supports the lens carrier upwardly in a thermally driven manner, and pulls the lens carrier to move upward; wherein the lens carrier is drivingly connected to the downgoing driver, and the downgoing driver draws the lens carrier downwardly in a thermally driven manner, and pulls the lens carrier to move downward; and wherein the lens is disposed on the lens carrier of the SMA driving device, and the SMA driving device drives the lens to move up and down, thereby improving the focusing speed of the lens.

Abstract: A driving route matching method, apparatus, and storage medium. The method includes: obtaining a route to be retrieved, the route including a retrieval start point and a retrieval end point; performing a search in a database of existing routes, and selecting the existing routes passing through grids within a predetermined range around the start point as routes available for the start point; performing a search in the database of the existing routes, and selecting the existing routes passing through grids within a predetermined range around the search endpoint as routes available for the end point; calculating intersections of the routes available for the start point and the routes available for the end point, and using the routes in the intersections as candidate routes; and screening the candidate routes according to detouring distances. The driving route matching method and apparatus enable a remarkable improvement in the efficiency of driving route matching.

Abstract: A method for data propagation analysis. A data propagation diagram for a circuit design is generated. The data propagation diagram includes a plurality of nodes and a plurality of edges connecting the nodes. The nodes represent data locations in the circuit design and the edges represent data propagation paths between the data locations in the circuit design. A signal trace specifying signal values for the circuit design is analyzed to determine whether data at a first data location of the data locations during a first clock cycle is causally related to the data at a second data location of the data locations during a second clock cycle. A visual animation is displayed on the data propagation diagram indicating movement of the data between a first node of the nodes corresponding to the first data location and a second node of the nodes corresponding to the second data location.

Abstract: A driving route matching method, apparatus, and storage medium. The method includes: obtaining a route to be retrieved, the route including a retrieval start point and a retrieval end point; performing a search in a database of existing routes, and selecting the existing routes passing through grids within a predetermined range around the start point as routes available for the start point; performing a search in the database of the existing routes, and selecting the existing routes passing through grids within a predetermined range around the search endpoint as routes available for the end point; calculating intersections of the routes available for the start point and the routes available for the end point, and using the routes in the intersections as candidate routes; and screening the candidate routes according to detouring distances. The driving route matching method and apparatus enable a remarkable improvement in the efficiency of driving route matching.

Abstract: Various mechanisms and approaches identify a first electronic design component at least by traversing at least a portion of the electronic design and generate a representation of the electronic design by interconnecting one or more duplicated electronic design components within the representation. The first electronic design component may include a destination electronic design component with a backward traversal of the electronic design. One or more fan-in electronic design components may be duplicated into the one or more duplicated electronic design components. One or more CDC effect models are automatically injected into the representation by adding the one or more CDC effect models along one or more paths in the representation. Proof results are generated at least via proving or disproving one or more checkers for the electronic design by verifying or simulating the representation with the one or more CDC effect models that are automatically injected into the representation.

Abstract: A method for data propagation analysis. A data propagation diagram for a circuit design is generated. The data propagation diagram includes a plurality of nodes and a plurality of edges connecting the nodes. The nodes represent data locations in the circuit design and the edges represent data propagation paths between the data locations in the circuit design. A signal trace specifying signal values for the circuit design is analyzed to determine whether data at a first data location of the data locations during a first clock cycle is causally related to the data at a second data location of the data locations during a second clock cycle. A visual animation is displayed on the data propagation diagram indicating movement of the data between a first node of the nodes corresponding to the first data location and a second node of the nodes corresponding to the second data location.

Abstract: A verification system determines proof of the absence of a deadlock condition or other data-transport property in a multi-system SoC using helper assertions derived from a transaction definition. The verification system receives the circuit design information along with a transaction definition for one or more ports of the SoC. Once specified, the transaction definition is instantiated into the full system or subsystem RTL, generating an expanded RTL and a deadlock property. Data flow through the RTL is analyzed to extract helper assertions describing how the data flowed through the RTL. Helper assertions are automatically extracted to aid in the verification of the absence of a deadlock condition. Using the helper assertions, the formal engine applies one or more techniques to formally analyze the circuit design to prove the absence of a deadlock condition.