Patents by Inventor Xiaoyao Liang

Xiaoyao Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Process variation tolerant circuit with voltage interpolation and variable latency
    Patent number: 7667497
    Abstract: A circuit having dynamically controllable power. The circuit comprises a plurality of pipelined stages, each of the pipelined stages comprising two clocking domains, a plurality of switching circuits, each switching circuit being connected to one of the pipelined stages, first and second power sources connected to each of the plurality of pipelined stages through the switching circuits, the first power source supplying a first voltage and the second power source supplying a second voltage, wherein the first and second power sources each may be applied to a pipelined stage independently of other pipelined stages, first and second complementary clocks, and a plurality of latches connected to the first and second complementary clocks and to the plurality of pipelined stages for proving latch-based clocking to control the first and second clocking domains and to enable time-borrowing across the plurality of switching circuits.
    Type: Grant
    Filed: October 30, 2008
    Date of Patent: February 23, 2010
    Assignee: President and Fellows of Harvard College
    Inventors: Xiaoyao Liang, David Brooks, Gu-Yeon Wei
  • Process Variation Tolerant Circuit With Voltage Interpolation And Variable Latency
    Publication number: 20090134707
    Abstract: A circuit having dynamically controllable power. The circuit comprises a plurality of pipelined stages, each of the pipelined stages comprising two clocking domains, a plurality of switching circuits, each switching circuit being connected to one of the pipelined stages, first and second power sources connected to each of the plurality of pipelined stages through the switching circuits, the first power source supplying a first voltage and the second power source supplying a second voltage, wherein the first and second power sources each may be applied to a pipelined stage independently of other pipelined stages, first and second complementary clocks, and a plurality of latches connected to the first and second complementary clocks and to the plurality of pipelined stages for proving latch-based clocking to control the first and second clocking domains and to enable time-borrowing across the plurality of switching circuits.
    Type: Application
    Filed: October 30, 2008
    Publication date: May 28, 2009
    Inventors: Xiaoyao Liang, David Brooks, Gu-Yeon Wei